Searched refs:szBlg2 (Results 1 – 3 of 3) sorted by relevance
/external/valgrind/VEX/priv/ |
D | guest_arm_toIR.c | 13169 UInt szBlg2 = 4; // invalid in decode_V8_instruction() local 13179 szBlg2 = INSN(5,4); // 00:B 01:H 10:W 11:invalid in decode_V8_instruction() 13180 gate = szBlg2 != BITS2(1,1) && tt != 15 && nn != 15; in decode_V8_instruction() 13188 szBlg2 = INSN(22,21); // 10:B 11:H 00:W 01:invalid in decode_V8_instruction() 13189 gate = szBlg2 != BITS2(0,1) && tt != 15 && nn != 15; in decode_V8_instruction() 13197 szBlg2 = INSN(22,21); // 10:B 11:H 00:W 01:invalid in decode_V8_instruction() 13198 gate = szBlg2 != BITS2(0,1) && tt != 15 && nn != 15; in decode_V8_instruction() 13202 switch (szBlg2) { in decode_V8_instruction() 13203 case 2: szBlg2 = 0; break; in decode_V8_instruction() 13204 case 3: szBlg2 = 1; break; in decode_V8_instruction() [all …]
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D | guest_arm64_toIR.c | 6495 UInt szBlg2 = INSN(31,30); in dis_ARM64_load_store() local 6502 vassert(szBlg2 < 4); in dis_ARM64_load_store() 6503 UInt szB = 1 << szBlg2; /* 1, 2, 4 or 8 */ in dis_ARM64_load_store() 6529 DIP("ld%sx%s %s, [%s] %s\n", isAcqOrRel ? "a" : "", suffix[szBlg2], in dis_ARM64_load_store() 6601 DIP("st%sx%s %s, %s, [%s] %s\n", isAcqOrRel ? "a" : "", suffix[szBlg2], in dis_ARM64_load_store() 6619 UInt szBlg2 = INSN(31,30); in dis_ARM64_load_store() local 6624 vassert(szBlg2 < 4); in dis_ARM64_load_store() 6625 UInt szB = 1 << szBlg2; /* 1, 2, 4 or 8 */ in dis_ARM64_load_store() 6638 DIP("lda%s %s, [%s]\n", suffix[szBlg2], in dis_ARM64_load_store() 6644 DIP("stl%s %s, [%s]\n", suffix[szBlg2], in dis_ARM64_load_store() [all …]
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/external/valgrind/ |
D | NEWS | 191 372794 LibVEX (arm32 front end): 'Assertion szBlg2 <= 3' failed
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