/external/boringssl/linux-aarch64/crypto/fipsmodule/ |
D | sha1-armv8.S | 33 ldr w24,[x0,#16] 45 add w24,w24,w28 // warm it up 46 add w24,w24,w3 54 add w24,w24,w27 // e+=rot(a,5) 57 add w24,w24,w25 // e+=F(b,c,d) 65 ror w27,w24,#27 74 bic w25,w21,w24 75 and w26,w20,w24 80 ror w24,w24,#2 89 and w26,w24,w23 [all …]
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D | sha256-armv8.S | 77 ldp w24,w25,[x0,#4*4] 91 ror w16,w24,#6 93 eor w6,w24,w24,ror#14 94 and w17,w25,w24 95 bic w19,w26,w24 119 and w17,w24,w23 144 bic w19,w24,w22 166 add w24,w24,w28 // h+=K[i] 170 add w24,w24,w6 // h+=X[i] 175 add w24,w24,w17 // h+=Ch(e,f,g) [all …]
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/external/boringssl/ios-aarch64/crypto/fipsmodule/ |
D | sha1-armv8.S | 32 ldr w24,[x0,#16] 44 add w24,w24,w28 // warm it up 45 add w24,w24,w3 53 add w24,w24,w27 // e+=rot(a,5) 56 add w24,w24,w25 // e+=F(b,c,d) 64 ror w27,w24,#27 73 bic w25,w21,w24 74 and w26,w20,w24 79 ror w24,w24,#2 88 and w26,w24,w23 [all …]
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D | sha256-armv8.S | 76 ldp w24,w25,[x0,#4*4] 90 ror w16,w24,#6 92 eor w6,w24,w24,ror#14 93 and w17,w25,w24 94 bic w19,w26,w24 118 and w17,w24,w23 143 bic w19,w24,w22 165 add w24,w24,w28 // h+=K[i] 169 add w24,w24,w6 // h+=X[i] 174 add w24,w24,w17 // h+=Ch(e,f,g) [all …]
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/external/llvm/test/MC/Mips/msa/ |
D | test_bit.s | 4 # CHECK: bclri.h $w24, $w21, 0 # encoding: [0x79,0xe0,0xae,0x09] 15 # CHECK: bnegi.b $w24, $w19, 0 # encoding: [0x7a,0xf0,0x9e,0x09] 20 # CHECK: bseti.h $w24, $w14, 2 # encoding: [0x7a,0x62,0x76,0x09] 28 # CHECK: sat_u.h $w30, $w24, 4 # encoding: [0x78,0xe4,0xc7,0x8a] 35 # CHECK: srai.b $w24, $w29, 1 # encoding: [0x78,0xf1,0xee,0x09] 50 # CHECK: srlri.d $w24, $w10, 6 # encoding: [0x79,0x86,0x56,0x0a] 53 bclri.h $w24, $w21, 0 64 bnegi.b $w24, $w19, 0 69 bseti.h $w24, $w14, 2 77 sat_u.h $w30, $w24, 4 [all …]
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D | test_i5.s | 4 # CHECK: addvi.h $w24, $w13, 26 # encoding: [0x78,0x3a,0x6e,0x06] 7 # CHECK: ceqi.b $w24, $w21, -8 # encoding: [0x78,0x18,0xae,0x07] 10 # CHECK: ceqi.d $w24, $w22, 7 # encoding: [0x78,0x67,0xb6,0x07] 24 # CHECK: clti_u.h $w24, $w25, 25 # encoding: [0x79,0xb9,0xce,0x07] 43 # CHECK: subvi.b $w24, $w20, 19 # encoding: [0x78,0x93,0xa6,0x06] 49 addvi.h $w24, $w13, 26 52 ceqi.b $w24, $w21, -8 55 ceqi.d $w24, $w22, 7 69 clti_u.h $w24, $w25, 25 88 subvi.b $w24, $w20, 19
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D | test_3rf.s | 9 # CHECK: fcle.w $w16, $w9, $w24 # encoding: [0x79,0x98,0x4c,0x1a] 27 # CHECK: fdiv.w $w13, $w24, $w2 # encoding: [0x78,0xc2,0xc3,0x5b] 39 # CHECK: fmin.w $w24, $w1, $w30 # encoding: [0x7b,0x1e,0x0e,0x1b] 42 # CHECK: fmin_a.d $w13, $w30, $w24 # encoding: [0x7b,0x78,0xf3,0x5b] 52 # CHECK: fsle.d $w18, $w23, $w24 # encoding: [0x7b,0xb8,0xbc,0x9a] 58 # CHECK: fsor.d $w12, $w24, $w11 # encoding: [0x7a,0x6b,0xc3,0x1c] 61 # CHECK: fsueq.w $w16, $w24, $w25 # encoding: [0x7a,0xd9,0xc4,0x1a] 71 # CHECK: ftq.h $w16, $w4, $w24 # encoding: [0x7a,0x98,0x24,0x1b] 77 # CHECK: msub_q.h $w24, $w26, $w10 # encoding: [0x79,0x8a,0xd6,0x1c] 92 fcle.w $w16, $w9, $w24 [all …]
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D | test_3r.s | 7 # CHECK: adds_a.b $w19, $w24, $w19 # encoding: [0x78,0x93,0xc4,0xd0] 19 # CHECK: addv.b $w24, $w20, $w21 # encoding: [0x78,0x15,0xa6,0x0e] 25 # CHECK: asub_s.w $w24, $w1, $w9 # encoding: [0x7a,0x49,0x0e,0x11] 51 # CHECK: binsl.b $w5, $w16, $w24 # encoding: [0x7b,0x18,0x81,0x4d] 59 # CHECK: bneg.b $w0, $w11, $w24 # encoding: [0x7a,0x98,0x58,0x0d] 85 # CHECK: clt_u.w $w3, $w24, $w9 # encoding: [0x79,0xc9,0xc0,0xcf] 92 # CHECK: div_u.h $w24, $w21, $w14 # encoding: [0x7a,0xae,0xae,0x12] 105 # CHECK: dpadd_u.w $w24, $w8, $w16 # encoding: [0x79,0xd0,0x46,0x13] 113 # CHECK: hadd_s.h $w28, $w24, $w2 # encoding: [0x7a,0x22,0xc7,0x15] 114 # CHECK: hadd_s.w $w24, $w17, $w11 # encoding: [0x7a,0x4b,0x8e,0x15] [all …]
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D | test_elm.s | 13 splati.h $w24, $w28[1] # CHECK: splati.h $w24, $w28[1] # encoding: [0x78,0x61,0xe6,0x19] 16 move.v $w23, $w24 # CHECK: move.v $w23, $w24 # encoding: [0x78,0xbe,0xc5,0xd9]
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D | test_i10.s | 5 # CHECK: ldi.w $w24, 492 # encoding: [0x7b,0x4f,0x66,0x07] 10 ldi.w $w24, 492
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D | test_elm_insve.s | 4 # CHECK: insve.h $w24[2], $w2[0] # encoding: [0x79,0x62,0x16,0x19] 9 insve.h $w24[2], $w2[0]
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D | test_vec.s | 8 # CHECK: or.v $w24, $w26, $w30 # encoding: [0x78,0x3e,0xd6,0x1e] 16 or.v $w24, $w26, $w30
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D | test_2r.s | 17 # CHECK: pcnt.d $w21, $w24 # encoding: [0x7b,0x07,0xc5,0x5e] 33 pcnt.d $w21, $w24
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D | test_2rf.s | 4 # CHECK: fclass.d $w24, $w17 # encoding: [0x7b,0x21,0x8e,0x1e] 37 fclass.d $w24, $w17
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D | invalid-64.s | 12 insve.h $w24[-1], $w2[0] # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate 13 insve.h $w24[8], $w2[0] # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate 19 insve.h $w24[2], $w2[1] # CHECK: :[[@LINE]]:26: error: expected '0'
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/external/llvm/test/MC/Disassembler/Mips/msa/ |
D | test_bit.txt | 4 0x79 0xe0 0xae 0x09 # CHECK: bclri.h $w24, $w21, 0 15 0x7a 0xf0 0x9e 0x09 # CHECK: bnegi.b $w24, $w19, 0 20 0x7a 0x62 0x76 0x09 # CHECK: bseti.h $w24, $w14, 2 28 0x78 0xe4 0xc7 0x8a # CHECK: sat_u.h $w30, $w24, 4 35 0x78 0xf1 0xee 0x09 # CHECK: srai.b $w24, $w29, 1 50 0x79 0x86 0x56 0x0a # CHECK: srlri.d $w24, $w10, 6
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D | test_3rf.txt | 9 0x79 0x98 0x4c 0x1a # CHECK: fcle.w $w16, $w9, $w24 27 0x78 0xc2 0xc3 0x5b # CHECK: fdiv.w $w13, $w24, $w2 39 0x7b 0x1e 0x0e 0x1b # CHECK: fmin.w $w24, $w1, $w30 42 0x7b 0x78 0xf3 0x5b # CHECK: fmin_a.d $w13, $w30, $w24 52 0x7b 0xb8 0xbc 0x9a # CHECK: fsle.d $w18, $w23, $w24 58 0x7a 0x6b 0xc3 0x1c # CHECK: fsor.d $w12, $w24, $w11 61 0x7a 0xd9 0xc4 0x1a # CHECK: fsueq.w $w16, $w24, $w25 71 0x7a 0x98 0x24 0x1b # CHECK: ftq.h $w16, $w4, $w24 77 0x79 0x8a 0xd6 0x1c # CHECK: msub_q.h $w24, $w26, $w10
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D | test_i5.txt | 4 0x78 0x3a 0x6e 0x06 # CHECK: addvi.h $w24, $w13, 26 7 0x78 0x18 0xae 0x07 # CHECK: ceqi.b $w24, $w21, 24 10 0x78 0x67 0xb6 0x07 # CHECK: ceqi.d $w24, $w22, 7 24 0x79 0xb9 0xce 0x07 # CHECK: clti_u.h $w24, $w25, 25 43 0x78 0x93 0xa6 0x06 # CHECK: subvi.b $w24, $w20, 19
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D | test_3r.txt | 7 0x78 0x93 0xc4 0xd0 # CHECK: adds_a.b $w19, $w24, $w19 19 0x78 0x15 0xa6 0x0e # CHECK: addv.b $w24, $w20, $w21 25 0x7a 0x49 0x0e 0x11 # CHECK: asub_s.w $w24, $w1, $w9 51 0x7b 0x18 0x81 0x4d # CHECK: binsl.b $w5, $w16, $w24 59 0x7a 0x98 0x58 0x0d # CHECK: bneg.b $w0, $w11, $w24 85 0x79 0xc9 0xc0 0xcf # CHECK: clt_u.w $w3, $w24, $w9 92 0x7a 0xae 0xae 0x12 # CHECK: div_u.h $w24, $w21, $w14 105 0x79 0xd0 0x46 0x13 # CHECK: dpadd_u.w $w24, $w8, $w16 113 0x7a 0x22 0xc7 0x15 # CHECK: hadd_s.h $w28, $w24, $w2 114 0x7a 0x4b 0x8e 0x15 # CHECK: hadd_s.w $w24, $w17, $w11 [all …]
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D | test_elm.txt | 13 0x78 0x61 0xe6 0x19 # CHECK: splati.h $w24, $w28[1] 16 0x78 0xbe 0xc5 0xd9 # CHECK: move.v $w23, $w24
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D | test_i10.txt | 5 0x7b 0x4f 0x66 0x07 # CHECK: ldi.w $w24, 492
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/external/llvm/test/MC/Mips/mips32r2/ |
D | invalid-msa.s | 24 …ffqr.d $w25,$w24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f… 44 …ftrunc_s.w $w24,$w7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f… 54 …nlzc.h $w24,$w24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f… 60 …pcnt.h $w20,$w24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
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/external/boringssl/src/crypto/fipsmodule/sha/ |
D | sha1-altivec.c | 241 const vec_uint32_t w24 = sched_16_31(vw + 6, w20, w16, w12, w8, k); in sha1_block_data_order() local 247 const vec_uint32_t w28 = sched_16_31(vw + 7, w24, w20, w16, w12, k); in sha1_block_data_order() 253 const vec_uint32_t w32 = sched_32_79(vw + 8, w28, w24, w16, w4, w0, k); in sha1_block_data_order() 266 const vec_uint32_t w40 = sched_32_79(vw + 10, w36, w32, w24, w12, w8, k); in sha1_block_data_order() 284 const vec_uint32_t w52 = sched_32_79(vw + 13, w48, w44, w36, w24, w20, k); in sha1_block_data_order() 290 const vec_uint32_t w56 = sched_32_79(vw + 14, w52, w48, w40, w28, w24, k); in sha1_block_data_order()
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/external/llvm/test/MC/AArch64/ |
D | arm64-leaf-compact-unwind.s | 131 .cfi_offset w24, -56 155 ldr w24, [x8] 172 add w9, w9, w24
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D | tls-relocs.s | 105 add w23, w24, #:dtprel_lo12:var 307 add w23, w24, #:tprel_lo12:var
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