| /external/llvm/test/MC/Disassembler/PowerPC/ |
| D | vsx.txt | 40 0xf0 0xe0 0xdd 0x64
43 0xf0 0xff 0xd8 0x04
46 0xf0 0xff 0xd9 0x04
55 0xf0 0xff 0xdd 0x84
58 0xf0 0xe0 0xdc 0x24
61 0xf0 0xe0 0xdc 0x2c
64 0xf0 0xe0 0xdd 0x60
67 0xf0 0xe0 0xd9 0x60
70 0xf0 0xe0 0xdd 0x20
73 0xf0 0xe0 0xd9 0x20
[all …]
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2-preloads.txt | 12 [0x91,0xf8,0x03,0xf0]
19 # MP-ERR-NEXT: [0xb3,0xf8,0x04,0xf0]
20 [0xb3,0xf8,0x04,0xf0]
28 [0x9f,0xf8,0x08,0xf0]
31 [0x1f,0xf8,0x05,0xf0]
34 [0x15,0xf8,0x06,0xf0]
37 [0x17,0xf8,0x18,0xf0]
41 # MP-ERR-NEXT: [0x39,0xf8,0x0a,0xf0]
42 [0x39,0xf8,0x0a,0xf0]
46 # MP-ERR-NEXT: [0x3b,0xf8,0x2c,0xf0]
[all …]
|
| D | crc32-thumb.txt | 10 0xc1 0xfa 0x82 0xf0
11 0xc1 0xfa 0x92 0xf0
12 0xc1 0xfa 0xa2 0xf0
13 0xd1 0xfa 0x82 0xf0
14 0xd1 0xfa 0x92 0xf0
15 0xd1 0xfa 0xa2 0xf0
|
| D | arm-tests.txt | 22 0x0e 0xf0 0xa0 0xe1
34 0x5f 0xf0 0x7f 0xf5
37 0x56 0xf0 0x7f 0xf5
40 0x4f 0xf0 0x7f 0xf5
43 0x4e 0xf0 0x7f 0xf5
46 0x6f 0xf0 0x7f 0xf5
94 0xf0 0x90 0xf1 0xe1
100 0xf0 0x20 0x01 0xfe
106 0xf5 0x71 0xf0 0x53
146 0x01 0x00 0xf0 0x00
[all …]
|
| D | unpredictable-MRS-arm.txt | 4 # CHECK: 0x00 0xf0 0x0f 0x01
5 0x00 0xf0 0x0f 0x01
8 # CHECK: 0x00 0xf0 0x4f 0x01
9 0x00 0xf0 0x4f 0x01
|
| D | basic-arm-instructions-v8.txt | 13 0x59 0xf0 0x7f 0xf5
14 0x51 0xf0 0x7f 0xf5
15 0x55 0xf0 0x7f 0xf5
16 0x5d 0xf0 0x7f 0xf5
22 0x05 0xf0 0x20 0xe3
|
| D | basic-arm-instructions.txt | 23 0xf0 0x10 0xa2 0xe2
407 0x1f 0xf0 0x7f 0xf5
509 0xf0 0xf0 0x20 0xe3
510 0xf5 0xf0 0x20 0xe3
511 0xff 0xf0 0x20 0xe3
535 0x50 0xf0 0x7f 0xf5
536 0x51 0xf0 0x7f 0xf5
537 0x52 0xf0 0x7f 0xf5
538 0x53 0xf0 0x7f 0xf5
539 0x54 0xf0 0x7f 0xf5
[all …]
|
| /external/llvm/test/MC/Disassembler/SystemZ/ |
| D | insns-z13.txt | 12 0xe7 0xff 0xff 0xff 0xf0 0x27
21 0xe7 0xff 0xf0 0x00 0x0e 0xf3
30 0xe7 0xff 0xf0 0x00 0x0e 0xf1
48 0xe7 0xff 0xf0 0x00 0x2e 0xf1
57 0xe7 0xff 0xf0 0x00 0x3e 0xf1
66 0xe7 0xff 0xf0 0x00 0x1e 0xf1
75 0xe7 0xff 0xf0 0x00 0x4e 0xf1
93 0xe7 0xff 0xf0 0x00 0x2e 0xf3
102 0xe7 0xff 0xf0 0x00 0x3e 0xf3
111 0xe7 0xff 0xf0 0x00 0x1e 0xf3
[all …]
|
| D | insns.txt | 14 0xb3 0x1a 0x00 0xf0
26 0xed 0x00 0xf0 0x00 0x00 0x1a
35 0xed 0xf0 0x00 0x00 0x00 0x1a
47 0xb3 0x0a 0x00 0xf0
59 0xed 0x00 0xf0 0x00 0x00 0x0a
68 0xed 0xf0 0x00 0x00 0x00 0x0a
113 0xb9 0x18 0x00 0xf0
137 0xe3 0x00 0xf0 0x00 0x00 0x18
146 0xe3 0xf0 0x00 0x00 0x00 0x18
188 0xb9 0x08 0x00 0xf0
[all …]
|
| D | insns-z13-bad.txt | 14 #CHECK-NEXT: 0xe7 0x00 0x00 0x00 0xf0 0x03
15 0xe7 0x00 0x00 0x00 0xf0 0x03
26 #CHECK-NEXT: 0xe7 0x00 0x00 0x00 0xf0 0x02
27 0xe7 0x00 0x00 0x00 0xf0 0x02
38 #CHECK-NEXT: 0xe7 0x00 0x00 0x00 0xf0 0x01
39 0xe7 0x00 0x00 0x00 0xf0 0x01
|
| /external/llvm/test/MC/Disassembler/XCore/ |
| D | xcore.txt | 77 0xf0 0x1f
119 0xf0 0x37
435 0x07 0xf0 0x83 0x76
441 0x64 0xf0 0x73 0x70
447 0x01 0xf0 0x81 0x79
453 0x01 0xf0 0xa5 0x7a
459 0x07 0xf0 0x48 0x60
465 0x9b 0xf0 0x89 0x63
477 0xcd 0xf0 0x81 0x67
483 0x0f 0xf0 0xe8 0x6a
[all …]
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | llvm.amdgcn.image.atomic.ll | 5 ;SI: image_atomic_swap v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x3c,0xf0,0x00…
6 ;VI: image_atomic_swap v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x40,0xf0,0x00…
16 ;SI: image_atomic_swap v2, v[0:1], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x3c,0xf0,0x00…
17 ;VI: image_atomic_swap v2, v[0:1], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x40,0xf0,0x00…
27 ;SI: image_atomic_swap v1, v0, s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x3c,0xf0,0x00,0x0…
28 ;VI: image_atomic_swap v1, v0, s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x40,0xf0,0x00,0x0…
38 …ap v[4:5], v[0:3], s[0:7] dmask:0x3 unorm glc ; encoding: [0x00,0x33,0x40,0xf0,0x00,0x04,0x00,0x00]
39 …ap v[4:5], v[0:3], s[0:7] dmask:0x3 unorm glc ; encoding: [0x00,0x33,0x44,0xf0,0x00,0x04,0x00,0x00]
50 ;SI: image_atomic_add v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x44,0xf0,0x00,…
51 ;VI: image_atomic_add v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x48,0xf0,0x00,…
[all …]
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | arm-tests.txt | 22 0x0e 0xf0 0xa0 0xe1
34 0x5f 0xf0 0x7f 0xf5
37 0x56 0xf0 0x7f 0xf5
40 0x4f 0xf0 0x7f 0xf5
43 0x4e 0xf0 0x7f 0xf5
46 0x6f 0xf0 0x7f 0xf5
76 0xf0 0x20 0x01 0xfe
82 0xf5 0x71 0xf0 0x53
122 0x01 0x00 0xf0 0x00
138 0xf0 0x40 0x2a 0xe9
[all …]
|
| D | basic-arm-instructions.txt | 20 0xf0 0x10 0xa2 0xe2
374 0x1f 0xf0 0x7f 0xf5
464 0xf0 0xf0 0x20 0xe3
465 0xf5 0xf0 0x20 0xe3
466 0xff 0xf0 0x20 0xe3
482 0x5f 0xf0 0x7f 0xf5
483 0x5e 0xf0 0x7f 0xf5
484 0x5b 0xf0 0x7f 0xf5
485 0x5a 0xf0 0x7f 0xf5
486 0x57 0xf0 0x7f 0xf5
[all …]
|
| D | neont2.txt | 20 0xf0 0xff 0x20 0x07
26 0xf0 0xff 0x60 0x07
248 0xf0 0xff 0x20 0x05
250 0xf0 0xff 0x60 0x05
252 0xf0 0xff 0xa0 0x04
258 0xf0 0xff 0xe0 0x04
264 0xf0 0xff 0x20 0x04
270 0xf0 0xff 0x60 0x04
313 0xf0 0xff 0xa0 0x05
315 0xf0 0xff 0xe0 0x05
[all …]
|
| D | neon.txt | 20 0x20 0x07 0xf0 0xf3
26 0x60 0x07 0xf0 0xf3
252 0x20 0x05 0xf0 0xf3
254 0x60 0x05 0xf0 0xf3
256 0xa0 0x04 0xf0 0xf3
262 0xe0 0x04 0xf0 0xf3
268 0x20 0x04 0xf0 0xf3
274 0x60 0x04 0xf0 0xf3
319 0xa0 0x05 0xf0 0xf3
321 0xe0 0x05 0xf0 0xf3
[all …]
|
| /external/llvm/test/CodeGen/X86/ |
| D | atomic16.ll | 18 ; X64: addw $3, {{.*}} # encoding: [0x66,0xf0
23 ; X64: xaddw {{.*}} # encoding: [0x66,0xf0
28 ; X64: addw {{.*}} # encoding: [0x66,0xf0
46 ; X64: subw $3, {{.*}} # encoding: [0x66,0xf0
51 ; X64: xaddw {{.*}} # encoding: [0x66,0xf0
56 ; X64: subw {{.*}} # encoding: [0x66,0xf0
69 ; X64: andw $3, {{.*}} # encoding: [0x66,0xf0
81 ; X64: andw {{.*}} # encoding: [0x66,0xf0
94 ; X64: orw $3, {{.*}} # encoding: [0x66,0xf0
106 ; X64: orw {{.*}} # encoding: [0x66,0xf0
[all …]
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | armv8.1a-rdma.txt | 42 [0x20,0xf0,0x32,0x2f] # sqrdmlsh v0.8b, v1.8b, v2.b[3]
44 [0x20,0xf0,0xe2,0x2f] # sqrdmlsh v0.1d, v1.1d, v2.d[1]
46 [0x20,0xf0,0x32,0x6f] # sqrdmlsh v0.16b, v1.16b, v2.b[3]
52 # CHECK: [0x20,0xf0,0x32,0x2f]
56 # CHECK: [0x20,0xf0,0xe2,0x2f]
60 # CHECK: [0x20,0xf0,0x32,0x6f]
67 [0x20,0xf0,0x32,0x7f] # sqrdmlsh b0, b1, v2.b[3]
73 # CHECK: [0x20,0xf0,0x32,0x7f]
106 0x20,0xf0,0x72,0x2f
108 0x20,0xf0,0xa2,0x2f
[all …]
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
| D | lock-inst-encoding.ll | 7 ; CHECK: addq %{{.*}}, ({{.*}}){{.*}}encoding: [0xf0,0x48,0x01,0x37]
15 ; CHECK: subq %{{.*}}, ({{.*}}){{.*}}encoding: [0xf0,0x48,0x29,0x37]
23 ; CHECK: andq %{{.*}}, ({{.*}}){{.*}}encoding: [0xf0,0x48,0x21,0x37]
31 ; CHECK: orq %{{.*}}, ({{.*}}){{.*}}encoding: [0xf0,0x48,0x09,0x37]
39 ; CHECK: xorq %{{.*}}, ({{.*}}){{.*}}encoding: [0xf0,0x48,0x31,0x37]
|
| /external/python/cpython2/Demo/tix/bitmaps/ |
| D | capital.xbm | 5 0x30, 0x03, 0xb0, 0x01, 0xf0, 0x00, 0xf0, 0x00, 0xf0, 0x01, 0xb0, 0x03,
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | prefetch.ll | 8 ; ARM: pldw [r0] @ encoding: [0x00,0xf0,0x90,0xf5]
9 ; ARM: pld [r0] @ encoding: [0x00,0xf0,0xd0,0xf5]
12 ; T2: pld [r0] @ encoding: [0x90,0xf8,0x00,0xf0]
36 ; T2: pld [r0, r1] @ encoding: [0x10,0xf8,0x01,0xf0]
50 ; T2: pld [r0, r1, lsl #2] @ encoding: [0x10,0xf8,0x21,0xf0]
|
| /external/llvm/test/MC/Disassembler/Hexagon/ |
| D | xtype_mpy.txt | 33 0xf0 0xde 0x14 0xe8
35 0xf0 0xde 0x94 0xe8
41 0xf0 0xde 0x34 0xe8
43 0xf0 0xde 0xb4 0xe8
49 0xf0 0xde 0x14 0xea
51 0xf0 0xde 0x94 0xea
57 0xf0 0xde 0x34 0xea
59 0xf0 0xde 0xb4 0xea
67 0xf0 0xde 0x54 0xe8
69 0xf0 0xde 0xd4 0xe8
[all …]
|
| D | xtype_complex.txt | 33 0xf0 0xdf 0x15 0xe7
35 0xf0 0xdf 0x95 0xe7
41 0xf0 0xdf 0x55 0xe7
43 0xf0 0xdf 0xd5 0xe7
91 0xf0 0xc0 0x94 0x80
125 0xf0 0xff 0xd4 0xc3
|
| /external/arm-neon-tests/ |
| D | expected_input4gcc-nofp16.txt | 3 VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 };
7 VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 };
11 VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 };
14 VECT_VAR_DECL(expected,int,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9,…
18 VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9…
22 VECT_VAR_DECL(expected,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9…
38 …,8,16) [] = { 0xe6, 0xe7, 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, 0xf0, 0xf1, 0xf2, 0xf3, …
53 VECT_VAR_DECL(expected,int,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xf0, 0xaa };
57 VECT_VAR_DECL(expected,uint,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xf0 };
61 VECT_VAR_DECL(expected,poly,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xf0 };
[all …]
|
| D | expected_input4gcc.txt | 3 VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 };
7 VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 };
11 VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 };
15 VECT_VAR_DECL(expected,int,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9,…
19 VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9…
23 VECT_VAR_DECL(expected,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9…
41 …,8,16) [] = { 0xe6, 0xe7, 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, 0xf0, 0xf1, 0xf2, 0xf3, …
57 VECT_VAR_DECL(expected,int,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xf0, 0xaa };
61 VECT_VAR_DECL(expected,uint,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xf0 };
65 VECT_VAR_DECL(expected,poly,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xf0 };
[all …]
|