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Name Date Size #Lines LOC

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Android.mkD03-May-20243 KiB7447

Init.sD03-May-202411.7 KiB260190

InitCache.sD03-May-20242.3 KiB5339

LICENSED03-May-2024204 119

MakefileD03-May-20246.8 KiB167102

Makefile.gccD03-May-20245.2 KiB12568

READMED03-May-20242.3 KiB6143

armscript.incD03-May-2024307 1510

compute_ref.axfD03-May-20243.4 MiB

compute_ref.cD03-May-20249.3 KiB371325

compute_ref.gccarmD03-May-20244.3 MiB

compute_ref.gccarm-rvctD03-May-20244.6 MiB

compute_ref_data.cD03-May-202421.6 KiB567499

expected_input4gcc-nofp16.txtD03-May-2024546.4 KiB7,0886,817

expected_input4gcc.txtD03-May-2024587.7 KiB7,6287,357

license.htmlD03-May-202425.4 KiB457455

ref-rvct-all.txtD03-May-2024571.9 KiB8,8348,425

ref-rvct-neon-nofp16.txtD03-May-2024494 KiB7,3576,962

ref-rvct-neon.txtD03-May-2024528.2 KiB7,9017,504

ref_dsp.cD03-May-202413 KiB422322

ref_dspfns.cD03-May-202448.7 KiB1,5031,165

ref_integer.cD03-May-20248.5 KiB291210

ref_v_binary_op.cD03-May-20242.9 KiB8944

ref_v_binary_sat_op.cD03-May-20243.9 KiB11164

ref_v_comp_f_op.cD03-May-20243 KiB9044

ref_v_comp_op.cD03-May-20247.8 KiB222153

ref_v_unary_op.cD03-May-20243 KiB9246

ref_v_unary_sat_op.cD03-May-20243.3 KiB9751

ref_vaba.cD03-May-20244.3 KiB12683

ref_vabal.cD03-May-20244.3 KiB12979

ref_vabd.cD03-May-20244.5 KiB13487

ref_vabdl.cD03-May-20243.1 KiB9452

ref_vabs.cD03-May-20241.8 KiB5520

ref_vadd.cD03-May-20241.9 KiB6124

ref_vaddhn.cD03-May-20243.2 KiB9553

ref_vaddl.cD03-May-20243.5 KiB10560

ref_vaddw.cD03-May-20243.5 KiB10560

ref_vand.cD03-May-20241.2 KiB303

ref_vbic.cD03-May-20241.2 KiB303

ref_vbsl.cD03-May-20243.8 KiB10562

ref_vcage.cD03-May-20241.2 KiB303

ref_vcagt.cD03-May-20241.2 KiB303

ref_vcale.cD03-May-20241.2 KiB303

ref_vcalt.cD03-May-20241.2 KiB303

ref_vceq.cD03-May-20242 KiB6425

ref_vcge.cD03-May-20241.2 KiB303

ref_vcgt.cD03-May-20241.2 KiB303

ref_vcle.cD03-May-20241.2 KiB303

ref_vcls.cD03-May-20243.7 KiB10858

ref_vclt.cD03-May-20241.2 KiB303

ref_vclz.cD03-May-20245.1 KiB14394

ref_vcnt.cD03-May-20243 KiB8945

ref_vcombine.cD03-May-20243.8 KiB10161

ref_vcreate.cD03-May-20244.2 KiB12076

ref_vcvt.cD03-May-20249 KiB237151

ref_vdup.cD03-May-20243.6 KiB11774

ref_vdup_lane.cD03-May-20242.9 KiB8242

ref_veor.cD03-May-20241.2 KiB303

ref_vext.cD03-May-20243.7 KiB10968

ref_vget_high.cD03-May-20242.8 KiB7741

ref_vget_lane.cD03-May-20243.8 KiB11064

ref_vget_low.cD03-May-20242.8 KiB7741

ref_vhadd.cD03-May-20241.2 KiB324

ref_vhsub.cD03-May-20241.2 KiB324

ref_vld1.cD03-May-20242.3 KiB6527

ref_vld1_dup.cD03-May-20242.4 KiB7031

ref_vld1_lane.cD03-May-20244.7 KiB13188

ref_vldX.cD03-May-20248 KiB222163

ref_vldX_dup.cD03-May-20247 KiB188133

ref_vldX_lane.cD03-May-20249.5 KiB244180

ref_vmax.cD03-May-20245.2 KiB15498

ref_vmin.cD03-May-20241.2 KiB303

ref_vmla.cD03-May-20244.9 KiB145101

ref_vmla_lane.cD03-May-20244.3 KiB12681

ref_vmla_n.cD03-May-20243.9 KiB11370

ref_vmlal.cD03-May-20244 KiB12073

ref_vmlal_lane.cD03-May-20243.5 KiB10258

ref_vmlal_n.cD03-May-20243 KiB9348

ref_vmls.cD03-May-20241.2 KiB303

ref_vmls_lane.cD03-May-20241.2 KiB303

ref_vmls_n.cD03-May-20241.2 KiB303

ref_vmlsl.cD03-May-20241.2 KiB303

ref_vmlsl_lane.cD03-May-20241.2 KiB303

ref_vmlsl_n.cD03-May-20241.2 KiB303

ref_vmovl.cD03-May-20242 KiB6125

ref_vmovn.cD03-May-20242 KiB6125

ref_vmul.cD03-May-20244.5 KiB13593

ref_vmul_lane.cD03-May-20243.7 KiB10662

ref_vmul_n.cD03-May-20243.1 KiB9251

ref_vmull.cD03-May-20242.8 KiB8245

ref_vmull_lane.cD03-May-20242.9 KiB8542

ref_vmull_n.cD03-May-20242.8 KiB8342

ref_vmvn.cD03-May-20244.3 KiB12177

ref_vneg.cD03-May-20241.8 KiB5520

ref_vorn.cD03-May-20241.2 KiB303

ref_vorr.cD03-May-20241.2 KiB303

ref_vpadal.cD03-May-20245.1 KiB14194

ref_vpadd.cD03-May-20243.2 KiB9753

ref_vpaddl.cD03-May-20244.1 KiB11470

ref_vpmax.cD03-May-20241.2 KiB303

ref_vpmin.cD03-May-20241.2 KiB303

ref_vqabs.cD03-May-20242.6 KiB7435

ref_vqadd.cD03-May-20245.6 KiB158103

ref_vqdmlal.cD03-May-20243.3 KiB9955

ref_vqdmlal_lane.cD03-May-20243.7 KiB10663

ref_vqdmlal_n.cD03-May-20243.1 KiB9349

ref_vqdmlsl.cD03-May-20241.2 KiB303

ref_vqdmlsl_lane.cD03-May-20241.2 KiB303

ref_vqdmlsl_n.cD03-May-20241.2 KiB303

ref_vqdmulh.cD03-May-20243.9 KiB11667

ref_vqdmulh_lane.cD03-May-20244.1 KiB11763

ref_vqdmulh_n.cD03-May-20243.8 KiB11162

ref_vqdmull.cD03-May-20243.2 KiB9450

ref_vqdmull_lane.cD03-May-20243.6 KiB11058

ref_vqdmull_n.cD03-May-20243.5 KiB10555

ref_vqmovn.cD03-May-20244 KiB11564

ref_vqmovun.cD03-May-20243.2 KiB9647

ref_vqneg.cD03-May-20242.6 KiB7435

ref_vqrdmulh.cD03-May-20244.7 KiB13683

ref_vqrdmulh_lane.cD03-May-20244.7 KiB13576

ref_vqrdmulh_n.cD03-May-20244.3 KiB12573

ref_vqrshl.cD03-May-202411.6 KiB304212

ref_vqrshrn_n.cD03-May-20244.8 KiB13577

ref_vqrshrun_n.cD03-May-20245 KiB14376

ref_vqshl.cD03-May-20249.1 KiB242163

ref_vqshl_n.cD03-May-20244.7 KiB13383

ref_vqshlu_n.cD03-May-20245.8 KiB15896

ref_vqshrn_n.cD03-May-20244.8 KiB13677

ref_vqshrun_n.cD03-May-20244 KiB11759

ref_vqsub.cD03-May-20245.7 KiB164106

ref_vraddhn.cD03-May-20241.2 KiB303

ref_vrecpe.cD03-May-20244.8 KiB14477

ref_vrecps.cD03-May-20243.9 KiB12159

ref_vreinterpret.cD03-May-202418.1 KiB399303

ref_vrev.cD03-May-20243.4 KiB10763

ref_vrhadd.cD03-May-20241.2 KiB324

ref_vrshl.cD03-May-20248 KiB221142

ref_vrshr_n.cD03-May-20248.1 KiB218153

ref_vrshrn_n.cD03-May-20244.2 KiB12067

ref_vrsqrte.cD03-May-20244.7 KiB14475

ref_vrsqrts.cD03-May-20243.9 KiB12159

ref_vrsra_n.cD03-May-20248.6 KiB239172

ref_vrsubhn.cD03-May-20241.2 KiB303

ref_vsXi_n.cD03-May-20244 KiB11772

ref_vset_lane.cD03-May-20243.1 KiB8344

ref_vshl.cD03-May-20243.4 KiB9950

ref_vshl_n.cD03-May-20242.5 KiB7636

ref_vshll_n.cD03-May-20242.2 KiB6526

ref_vshr_n.cD03-May-20242.6 KiB7736

ref_vshrn_n.cD03-May-20242.8 KiB8241

ref_vsli_n.cD03-May-20243.5 KiB9754

ref_vsra_n.cD03-May-20243.3 KiB9854

ref_vsri_n.cD03-May-20243.6 KiB9754

ref_vst1_lane.cD03-May-20243.1 KiB8650

ref_vstX_lane.cD03-May-20249.4 KiB244180

ref_vsub.cD03-May-20241.9 KiB6124

ref_vsubhn.cD03-May-20241.2 KiB303

ref_vsubl.cD03-May-20241.2 KiB303

ref_vsubw.cD03-May-20241.2 KiB303

ref_vtbX.cD03-May-20246.8 KiB228143

ref_vtrn.cD03-May-20241.2 KiB303

ref_vtst.cD03-May-20243.5 KiB10051

ref_vuzp.cD03-May-20246 KiB172115

ref_vzip.cD03-May-20241.2 KiB303

retarget.cD03-May-20241.1 KiB4722

scatter.scatD03-May-2024817 3020

stm-arm-neon-ref.hD03-May-202429 KiB816672

README

1ARM Neon reference tests
2========================
3This package contains extensive tests for the ARM/Neon instructions.
4
5It works by building a program which uses all of them, and then
6executing it on an actual target or a simulator.
7
8It can be used to validate the simulator against an actual HW target,
9or to validate C compilers in presence of Neon intrinsics calls.
10
11The supplied Makefile enables to build with both ARM RVCT compiler and
12GNU GCC (for the ARM target), and supports execution with ARM RVDEBUG
13on an ARM simulator and with QEMU.
14
15For convenience, the ARM ELF binary file (as compiled with RVCT) is
16supplied (compute_ref.axf), as well as expected output (ref-rvct.txt).
17
18A second file containing expected output is also supplied:
19ref-rvct-neon.txt, which contains only the results of the Neon
20instrinsics tests. It is aimed at being used to check GCC's results,
21since this compiler does not support the integer & dsp builtins whose
22results are also present in ref-rvct.txt.
23
24Typical usage when used to debug QEmu:
25$ make all # to build the test program with ARM rvct and execute with QEmu
26$ make check # to compare the results with the expected output
27
28
29Known issues:
30-------------
31Some tests currently fail to build with GCC/ARM:
32- missing include files: dspfns.h, armdsp.h
33
34As GCC/ARM provides no support for the
35Neon_Cumulative_Saturation/fpsrc register, auxiliary accessor
36functions have been implemented in stm-arm-neon-ref.h.
37
38Engineering:
39------------
40In order to cover all the Neon instructions extensively, these tests
41make intensive use of the C-preprocessor, to save maintenance efforts.
42
43Most tests (the more regular ones) share a common basic structure. In
44general, variable names are suffixed by their type name, so as to
45differentiate variables with the same purpose but of differente types.
46Hence vector1_int8x8, vector1_int16x4 etc...
47
48For instance in ref_vmul.c the layout of the code is as follows:
49
50- declare input and output vectors (named 'vector1', 'vector2' and
51  'vector_res') of each possible type (s/u, 8/16/32/64 bits).
52
53- clean the result buffers.
54
55- initialize input vectors 'vector1' and 'vector2'.
56
57- call each variant of the intrinsic and store the result in a buffer
58  named 'buffer', whose contents is printed after execution.
59
60One can then compare the actual result with the expected one.
61