1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #ifdef HAVE_CONFIG_H
25 #include "config.h"
26 #endif
27
28 #include <stdio.h>
29 #include <inttypes.h>
30
31 #include "CUnit/Basic.h"
32
33 #include "util_math.h"
34
35 #include "amdgpu_test.h"
36 #include "amdgpu_drm.h"
37 #include "amdgpu_internal.h"
38
39 #include "vce_ib.h"
40 #include "frame.h"
41
42 #define IB_SIZE 4096
43 #define MAX_RESOURCES 16
44
45 struct amdgpu_vce_bo {
46 amdgpu_bo_handle handle;
47 amdgpu_va_handle va_handle;
48 uint64_t addr;
49 uint64_t size;
50 uint8_t *ptr;
51 };
52
53 struct amdgpu_vce_encode {
54 unsigned width;
55 unsigned height;
56 struct amdgpu_vce_bo vbuf;
57 struct amdgpu_vce_bo bs[2];
58 struct amdgpu_vce_bo fb[2];
59 struct amdgpu_vce_bo cpb;
60 unsigned ib_len;
61 bool two_instance;
62 };
63
64 static amdgpu_device_handle device_handle;
65 static uint32_t major_version;
66 static uint32_t minor_version;
67 static uint32_t family_id;
68 static uint32_t vce_harvest_config;
69
70 static amdgpu_context_handle context_handle;
71 static amdgpu_bo_handle ib_handle;
72 static amdgpu_va_handle ib_va_handle;
73 static uint64_t ib_mc_address;
74 static uint32_t *ib_cpu;
75
76 static struct amdgpu_vce_encode enc;
77 static amdgpu_bo_handle resources[MAX_RESOURCES];
78 static unsigned num_resources;
79
80 static void amdgpu_cs_vce_create(void);
81 static void amdgpu_cs_vce_encode(void);
82 static void amdgpu_cs_vce_destroy(void);
83
84 CU_TestInfo vce_tests[] = {
85 { "VCE create", amdgpu_cs_vce_create },
86 { "VCE encode", amdgpu_cs_vce_encode },
87 { "VCE destroy", amdgpu_cs_vce_destroy },
88 CU_TEST_INFO_NULL,
89 };
90
suite_vce_tests_init(void)91 int suite_vce_tests_init(void)
92 {
93 int r;
94
95 r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
96 &minor_version, &device_handle);
97 if (r) {
98 if ((r == -EACCES) && (errno == EACCES))
99 printf("\n\nError:%s. "
100 "Hint:Try to run this test program as root.",
101 strerror(errno));
102
103 return CUE_SINIT_FAILED;
104 }
105
106 family_id = device_handle->info.family_id;
107 vce_harvest_config = device_handle->info.vce_harvest_config;
108
109 r = amdgpu_cs_ctx_create(device_handle, &context_handle);
110 if (r)
111 return CUE_SINIT_FAILED;
112
113 r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
114 AMDGPU_GEM_DOMAIN_GTT, 0,
115 &ib_handle, (void**)&ib_cpu,
116 &ib_mc_address, &ib_va_handle);
117 if (r)
118 return CUE_SINIT_FAILED;
119
120 memset(&enc, 0, sizeof(struct amdgpu_vce_encode));
121
122 return CUE_SUCCESS;
123 }
124
suite_vce_tests_clean(void)125 int suite_vce_tests_clean(void)
126 {
127 int r;
128
129 r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
130 ib_mc_address, IB_SIZE);
131 if (r)
132 return CUE_SCLEAN_FAILED;
133
134 r = amdgpu_cs_ctx_free(context_handle);
135 if (r)
136 return CUE_SCLEAN_FAILED;
137
138 r = amdgpu_device_deinitialize(device_handle);
139 if (r)
140 return CUE_SCLEAN_FAILED;
141
142 return CUE_SUCCESS;
143 }
144
submit(unsigned ndw,unsigned ip)145 static int submit(unsigned ndw, unsigned ip)
146 {
147 struct amdgpu_cs_request ibs_request = {0};
148 struct amdgpu_cs_ib_info ib_info = {0};
149 struct amdgpu_cs_fence fence_status = {0};
150 uint32_t expired;
151 int r;
152
153 ib_info.ib_mc_address = ib_mc_address;
154 ib_info.size = ndw;
155
156 ibs_request.ip_type = ip;
157
158 r = amdgpu_bo_list_create(device_handle, num_resources, resources,
159 NULL, &ibs_request.resources);
160 if (r)
161 return r;
162
163 ibs_request.number_of_ibs = 1;
164 ibs_request.ibs = &ib_info;
165 ibs_request.fence_info.handle = NULL;
166
167 r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
168 if (r)
169 return r;
170
171 r = amdgpu_bo_list_destroy(ibs_request.resources);
172 if (r)
173 return r;
174
175 fence_status.context = context_handle;
176 fence_status.ip_type = ip;
177 fence_status.fence = ibs_request.seq_no;
178
179 r = amdgpu_cs_query_fence_status(&fence_status,
180 AMDGPU_TIMEOUT_INFINITE,
181 0, &expired);
182 if (r)
183 return r;
184
185 return 0;
186 }
187
alloc_resource(struct amdgpu_vce_bo * vce_bo,unsigned size,unsigned domain)188 static void alloc_resource(struct amdgpu_vce_bo *vce_bo, unsigned size, unsigned domain)
189 {
190 struct amdgpu_bo_alloc_request req = {0};
191 amdgpu_bo_handle buf_handle;
192 amdgpu_va_handle va_handle;
193 uint64_t va = 0;
194 int r;
195
196 req.alloc_size = ALIGN(size, 4096);
197 req.preferred_heap = domain;
198 r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
199 CU_ASSERT_EQUAL(r, 0);
200 r = amdgpu_va_range_alloc(device_handle,
201 amdgpu_gpu_va_range_general,
202 req.alloc_size, 1, 0, &va,
203 &va_handle, 0);
204 CU_ASSERT_EQUAL(r, 0);
205 r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
206 AMDGPU_VA_OP_MAP);
207 CU_ASSERT_EQUAL(r, 0);
208 vce_bo->addr = va;
209 vce_bo->handle = buf_handle;
210 vce_bo->size = req.alloc_size;
211 vce_bo->va_handle = va_handle;
212 r = amdgpu_bo_cpu_map(vce_bo->handle, (void **)&vce_bo->ptr);
213 CU_ASSERT_EQUAL(r, 0);
214 memset(vce_bo->ptr, 0, size);
215 r = amdgpu_bo_cpu_unmap(vce_bo->handle);
216 CU_ASSERT_EQUAL(r, 0);
217 }
218
free_resource(struct amdgpu_vce_bo * vce_bo)219 static void free_resource(struct amdgpu_vce_bo *vce_bo)
220 {
221 int r;
222
223 r = amdgpu_bo_va_op(vce_bo->handle, 0, vce_bo->size,
224 vce_bo->addr, 0, AMDGPU_VA_OP_UNMAP);
225 CU_ASSERT_EQUAL(r, 0);
226
227 r = amdgpu_va_range_free(vce_bo->va_handle);
228 CU_ASSERT_EQUAL(r, 0);
229
230 r = amdgpu_bo_free(vce_bo->handle);
231 CU_ASSERT_EQUAL(r, 0);
232 memset(vce_bo, 0, sizeof(*vce_bo));
233 }
234
amdgpu_cs_vce_create(void)235 static void amdgpu_cs_vce_create(void)
236 {
237 int len, r;
238
239 enc.width = vce_create[6];
240 enc.height = vce_create[7];
241
242 num_resources = 0;
243 alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT);
244 resources[num_resources++] = enc.fb[0].handle;
245 resources[num_resources++] = ib_handle;
246
247 len = 0;
248 memcpy(ib_cpu, vce_session, sizeof(vce_session));
249 len += sizeof(vce_session) / 4;
250 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
251 len += sizeof(vce_taskinfo) / 4;
252 memcpy((ib_cpu + len), vce_create, sizeof(vce_create));
253 len += sizeof(vce_create) / 4;
254 memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback));
255 ib_cpu[len + 2] = enc.fb[0].addr >> 32;
256 ib_cpu[len + 3] = enc.fb[0].addr;
257 len += sizeof(vce_feedback) / 4;
258
259 r = submit(len, AMDGPU_HW_IP_VCE);
260 CU_ASSERT_EQUAL(r, 0);
261
262 free_resource(&enc.fb[0]);
263 }
264
amdgpu_cs_vce_config(void)265 static void amdgpu_cs_vce_config(void)
266 {
267 int len = 0, r;
268
269 memcpy((ib_cpu + len), vce_session, sizeof(vce_session));
270 len += sizeof(vce_session) / 4;
271 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
272 ib_cpu[len + 3] = 2;
273 ib_cpu[len + 6] = 0xffffffff;
274 len += sizeof(vce_taskinfo) / 4;
275 memcpy((ib_cpu + len), vce_rate_ctrl, sizeof(vce_rate_ctrl));
276 len += sizeof(vce_rate_ctrl) / 4;
277 memcpy((ib_cpu + len), vce_config_ext, sizeof(vce_config_ext));
278 len += sizeof(vce_config_ext) / 4;
279 memcpy((ib_cpu + len), vce_motion_est, sizeof(vce_motion_est));
280 len += sizeof(vce_motion_est) / 4;
281 memcpy((ib_cpu + len), vce_rdo, sizeof(vce_rdo));
282 len += sizeof(vce_rdo) / 4;
283 memcpy((ib_cpu + len), vce_pic_ctrl, sizeof(vce_pic_ctrl));
284 len += sizeof(vce_pic_ctrl) / 4;
285
286 r = submit(len, AMDGPU_HW_IP_VCE);
287 CU_ASSERT_EQUAL(r, 0);
288 }
289
amdgpu_cs_vce_encode_idr(struct amdgpu_vce_encode * enc)290 static void amdgpu_cs_vce_encode_idr(struct amdgpu_vce_encode *enc)
291 {
292
293 uint64_t luma_offset, chroma_offset;
294 int len = 0, r;
295
296 luma_offset = enc->vbuf.addr;
297 chroma_offset = luma_offset + enc->width * enc->height;
298
299 memcpy((ib_cpu + len), vce_session, sizeof(vce_session));
300 len += sizeof(vce_session) / 4;
301 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
302 len += sizeof(vce_taskinfo) / 4;
303 memcpy((ib_cpu + len), vce_bs_buffer, sizeof(vce_bs_buffer));
304 ib_cpu[len + 2] = enc->bs[0].addr >> 32;
305 ib_cpu[len + 3] = enc->bs[0].addr;
306 len += sizeof(vce_bs_buffer) / 4;
307 memcpy((ib_cpu + len), vce_context_buffer, sizeof(vce_context_buffer));
308 ib_cpu[len + 2] = enc->cpb.addr >> 32;
309 ib_cpu[len + 3] = enc->cpb.addr;
310 len += sizeof(vce_context_buffer) / 4;
311 memcpy((ib_cpu + len), vce_aux_buffer, sizeof(vce_aux_buffer));
312 len += sizeof(vce_aux_buffer) / 4;
313 memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback));
314 ib_cpu[len + 2] = enc->fb[0].addr >> 32;
315 ib_cpu[len + 3] = enc->fb[0].addr;
316 len += sizeof(vce_feedback) / 4;
317 memcpy((ib_cpu + len), vce_encode, sizeof(vce_encode));
318 ib_cpu[len + 9] = luma_offset >> 32;
319 ib_cpu[len + 10] = luma_offset;
320 ib_cpu[len + 11] = chroma_offset >> 32;
321 ib_cpu[len + 12] = chroma_offset;
322 ib_cpu[len + 73] = 0x7800;
323 ib_cpu[len + 74] = 0x7800 + 0x5000;
324 len += sizeof(vce_encode) / 4;
325 enc->ib_len = len;
326 if (!enc->two_instance) {
327 r = submit(len, AMDGPU_HW_IP_VCE);
328 CU_ASSERT_EQUAL(r, 0);
329 }
330 }
331
amdgpu_cs_vce_encode_p(struct amdgpu_vce_encode * enc)332 static void amdgpu_cs_vce_encode_p(struct amdgpu_vce_encode *enc)
333 {
334 uint64_t luma_offset, chroma_offset;
335 int len, r;
336
337 len = (enc->two_instance) ? enc->ib_len : 0;
338 luma_offset = enc->vbuf.addr;
339 chroma_offset = luma_offset + enc->width * enc->height;
340
341 if (!enc->two_instance) {
342 memcpy((ib_cpu + len), vce_session, sizeof(vce_session));
343 len += sizeof(vce_session) / 4;
344 }
345 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
346 len += sizeof(vce_taskinfo) / 4;
347 memcpy((ib_cpu + len), vce_bs_buffer, sizeof(vce_bs_buffer));
348 ib_cpu[len + 2] = enc->bs[1].addr >> 32;
349 ib_cpu[len + 3] = enc->bs[1].addr;
350 len += sizeof(vce_bs_buffer) / 4;
351 memcpy((ib_cpu + len), vce_context_buffer, sizeof(vce_context_buffer));
352 ib_cpu[len + 2] = enc->cpb.addr >> 32;
353 ib_cpu[len + 3] = enc->cpb.addr;
354 len += sizeof(vce_context_buffer) / 4;
355 memcpy((ib_cpu + len), vce_aux_buffer, sizeof(vce_aux_buffer));
356 len += sizeof(vce_aux_buffer) / 4;
357 memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback));
358 ib_cpu[len + 2] = enc->fb[1].addr >> 32;
359 ib_cpu[len + 3] = enc->fb[1].addr;
360 len += sizeof(vce_feedback) / 4;
361 memcpy((ib_cpu + len), vce_encode, sizeof(vce_encode));
362 ib_cpu[len + 2] = 0;
363 ib_cpu[len + 9] = luma_offset >> 32;
364 ib_cpu[len + 10] = luma_offset;
365 ib_cpu[len + 11] = chroma_offset >> 32;
366 ib_cpu[len + 12] = chroma_offset;
367 ib_cpu[len + 18] = 0;
368 ib_cpu[len + 19] = 0;
369 ib_cpu[len + 56] = 3;
370 ib_cpu[len + 57] = 0;
371 ib_cpu[len + 58] = 0;
372 ib_cpu[len + 59] = 0x7800;
373 ib_cpu[len + 60] = 0x7800 + 0x5000;
374 ib_cpu[len + 73] = 0;
375 ib_cpu[len + 74] = 0x5000;
376 ib_cpu[len + 81] = 1;
377 ib_cpu[len + 82] = 1;
378 len += sizeof(vce_encode) / 4;
379
380 r = submit(len, AMDGPU_HW_IP_VCE);
381 CU_ASSERT_EQUAL(r, 0);
382 }
383
check_result(struct amdgpu_vce_encode * enc)384 static void check_result(struct amdgpu_vce_encode *enc)
385 {
386 uint64_t sum;
387 uint32_t s[2] = {180325, 15946};
388 uint32_t *ptr, size;
389 int i, j, r;
390
391 for (i = 0; i < 2; ++i) {
392 r = amdgpu_bo_cpu_map(enc->fb[i].handle, (void **)&enc->fb[i].ptr);
393 CU_ASSERT_EQUAL(r, 0);
394 ptr = (uint32_t *)enc->fb[i].ptr;
395 size = ptr[4] - ptr[9];
396 r = amdgpu_bo_cpu_unmap(enc->fb[i].handle);
397 CU_ASSERT_EQUAL(r, 0);
398 r = amdgpu_bo_cpu_map(enc->bs[i].handle, (void **)&enc->bs[i].ptr);
399 CU_ASSERT_EQUAL(r, 0);
400 for (j = 0, sum = 0; j < size; ++j)
401 sum += enc->bs[i].ptr[j];
402 CU_ASSERT_EQUAL(sum, s[i]);
403 r = amdgpu_bo_cpu_unmap(enc->bs[i].handle);
404 CU_ASSERT_EQUAL(r, 0);
405 }
406 }
407
amdgpu_cs_vce_encode(void)408 static void amdgpu_cs_vce_encode(void)
409 {
410 uint32_t vbuf_size, bs_size = 0x154000, cpb_size;
411 int r;
412
413 vbuf_size = enc.width * enc.height * 1.5;
414 cpb_size = vbuf_size * 10;
415 num_resources = 0;
416 alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT);
417 resources[num_resources++] = enc.fb[0].handle;
418 alloc_resource(&enc.fb[1], 4096, AMDGPU_GEM_DOMAIN_GTT);
419 resources[num_resources++] = enc.fb[1].handle;
420 alloc_resource(&enc.bs[0], bs_size, AMDGPU_GEM_DOMAIN_GTT);
421 resources[num_resources++] = enc.bs[0].handle;
422 alloc_resource(&enc.bs[1], bs_size, AMDGPU_GEM_DOMAIN_GTT);
423 resources[num_resources++] = enc.bs[1].handle;
424 alloc_resource(&enc.vbuf, vbuf_size, AMDGPU_GEM_DOMAIN_VRAM);
425 resources[num_resources++] = enc.vbuf.handle;
426 alloc_resource(&enc.cpb, cpb_size, AMDGPU_GEM_DOMAIN_VRAM);
427 resources[num_resources++] = enc.cpb.handle;
428 resources[num_resources++] = ib_handle;
429
430 r = amdgpu_bo_cpu_map(enc.vbuf.handle, (void **)&enc.vbuf.ptr);
431 CU_ASSERT_EQUAL(r, 0);
432 memcpy(enc.vbuf.ptr, frame, sizeof(frame));
433 r = amdgpu_bo_cpu_unmap(enc.vbuf.handle);
434 CU_ASSERT_EQUAL(r, 0);
435
436 amdgpu_cs_vce_config();
437
438 if (family_id >= AMDGPU_FAMILY_VI) {
439 vce_taskinfo[3] = 3;
440 amdgpu_cs_vce_encode_idr(&enc);
441 amdgpu_cs_vce_encode_p(&enc);
442 check_result(&enc);
443
444 /* two pipes */
445 vce_encode[16] = 0;
446 amdgpu_cs_vce_encode_idr(&enc);
447 amdgpu_cs_vce_encode_p(&enc);
448 check_result(&enc);
449
450 /* two instances */
451 if (vce_harvest_config == 0) {
452 enc.two_instance = true;
453 vce_taskinfo[2] = 0x83;
454 vce_taskinfo[4] = 1;
455 amdgpu_cs_vce_encode_idr(&enc);
456 vce_taskinfo[2] = 0xffffffff;
457 vce_taskinfo[4] = 2;
458 amdgpu_cs_vce_encode_p(&enc);
459 check_result(&enc);
460 }
461 } else {
462 vce_taskinfo[3] = 3;
463 vce_encode[16] = 0;
464 amdgpu_cs_vce_encode_idr(&enc);
465 amdgpu_cs_vce_encode_p(&enc);
466 check_result(&enc);
467 }
468
469 free_resource(&enc.fb[0]);
470 free_resource(&enc.fb[1]);
471 free_resource(&enc.bs[0]);
472 free_resource(&enc.bs[1]);
473 free_resource(&enc.vbuf);
474 free_resource(&enc.cpb);
475 }
476
amdgpu_cs_vce_destroy(void)477 static void amdgpu_cs_vce_destroy(void)
478 {
479 int len, r;
480
481 num_resources = 0;
482 alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT);
483 resources[num_resources++] = enc.fb[0].handle;
484 resources[num_resources++] = ib_handle;
485
486 len = 0;
487 memcpy(ib_cpu, vce_session, sizeof(vce_session));
488 len += sizeof(vce_session) / 4;
489 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
490 ib_cpu[len + 3] = 1;
491 len += sizeof(vce_taskinfo) / 4;
492 memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback));
493 ib_cpu[len + 2] = enc.fb[0].addr >> 32;
494 ib_cpu[len + 3] = enc.fb[0].addr;
495 len += sizeof(vce_feedback) / 4;
496 memcpy((ib_cpu + len), vce_destroy, sizeof(vce_destroy));
497 len += sizeof(vce_destroy) / 4;
498
499 r = submit(len, AMDGPU_HW_IP_VCE);
500 CU_ASSERT_EQUAL(r, 0);
501
502 free_resource(&enc.fb[0]);
503 }
504