1; RUN: llc -O0 -march=hexagon -mcpu=hexagonv60 < %s | FileCheck %s 2 3; CHECK: vmem 4 5target triple = "hexagon" 6 7@vecpreds = external global [15 x <16 x i32>], align 64 8@vectors = external global [15 x <16 x i32>], align 64 9@vector_pairs = external global [15 x <32 x i32>], align 128 10@.str1 = external hidden unnamed_addr constant [20 x i8], align 1 11@.str2 = external hidden unnamed_addr constant [43 x i8], align 1 12@Q6VecPredResult = external global <16 x i32>, align 64 13@.str52 = external hidden unnamed_addr constant [57 x i8], align 1 14@.str54 = external hidden unnamed_addr constant [59 x i8], align 1 15@VectorResult = external global <16 x i32>, align 64 16@.str243 = external hidden unnamed_addr constant [60 x i8], align 1 17@.str251 = external hidden unnamed_addr constant [77 x i8], align 1 18@.str290 = external hidden unnamed_addr constant [65 x i8], align 1 19@VectorPairResult = external global <32 x i32>, align 128 20 21; Function Attrs: nounwind 22declare void @print_vector(i32, i8*) #0 23 24; Function Attrs: nounwind 25declare i32 @printf(i8*, ...) #0 26 27; Function Attrs: nounwind 28declare void @print_vecpred(i32, i8*) #0 29 30; Function Attrs: nounwind readnone 31declare <16 x i32> @llvm.hexagon.V6.vandqrt(<512 x i1>, i32) #1 32 33; Function Attrs: nounwind 34declare void @init_vectors() #0 35 36; Function Attrs: nounwind readnone 37declare <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #1 38 39; Function Attrs: nounwind readnone 40declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1 41 42; Function Attrs: nounwind 43declare void @init_addresses() #0 44 45; Function Attrs: nounwind 46declare <16 x i32> @llvm.hexagon.V6.vsubhnq(<512 x i1>, <16 x i32>, <16 x i32>) #1 47 48; Function Attrs: nounwind 49define i32 @main() #0 { 50entry: 51 %0 = load <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vecpreds, i32 0, i32 0), align 64 52 %1 = load <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vectors, i32 0, i32 1), align 64 53 call void @print_vecpred(i32 64, i8* bitcast (<16 x i32>* @Q6VecPredResult to i8*)) 54 %2 = load <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vectors, i32 0, i32 1), align 64 55 %call50 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([57 x i8], [57 x i8]* @.str52, i32 0, i32 0)) #3 56 %3 = load <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vectors, i32 0, i32 1), align 64 57 %call52 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([59 x i8], [59 x i8]* @.str54, i32 0, i32 0)) #3 58 %4 = load <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vectors, i32 0, i32 1), align 64 59 %call300 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([65 x i8], [65 x i8]* @.str290, i32 0, i32 0)) #3 60 %5 = load <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vectors, i32 0, i32 0), align 64 61 %6 = load <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vectors, i32 0, i32 1), align 64 62 %call1373 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([20 x i8], [20 x i8]* @.str1, i32 0, i32 0), i8* getelementptr inbounds ([43 x i8], [43 x i8]* @.str2, i32 0, i32 0), i8* getelementptr inbounds ([60 x i8], [60 x i8]* @.str243, i32 0, i32 0)) #3 63 %7 = call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1) 64 %call1381 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([20 x i8], [20 x i8]* @.str1, i32 0, i32 0), i8* getelementptr inbounds ([43 x i8], [43 x i8]* @.str2, i32 0, i32 0), i8* getelementptr inbounds ([77 x i8], [77 x i8]* @.str251, i32 0, i32 0)) #3 65 %8 = call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1) 66 %9 = call <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %8, i32 16843009) 67 call void @print_vector(i32 64, i8* bitcast (<16 x i32>* @VectorResult to i8*)) 68 %10 = call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1) 69 %11 = call <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %10, i32 16843009) 70 %12 = bitcast <512 x i1> %11 to <16 x i32> 71 %13 = bitcast <16 x i32> %12 to <512 x i1> 72 %14 = call <16 x i32> @llvm.hexagon.V6.vsubhnq(<512 x i1> %13, <16 x i32> undef, <16 x i32> undef) 73 store <16 x i32> %14, <16 x i32>* @VectorResult, align 64 74 ret i32 0 75} 76 77attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } 78attributes #1 = { nounwind readnone } 79attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } 80attributes #3 = { nounwind } 81