1; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx < %s \ 2; RUN: | FileCheck %s 3 4; Check that the store to Q6VecPredResult does not get expanded into multiple 5; stores. There should be no memd's. This relies on the alignment specified 6; in the data layout string, so don't provide one here to make sure that the 7; default one from HexagonTargetMachine is correct. 8 9; CHECK-NOT: memd 10 11 12@Q6VecPredResult = common global <16 x i32> zeroinitializer, align 64 13 14; Function Attrs: nounwind 15define i32 @foo() #0 { 16entry: 17 %0 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1) 18 %1 = tail call <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %0, i32 -2147483648) 19 store <512 x i1> %1, <512 x i1>* bitcast (<16 x i32>* @Q6VecPredResult to <512 x i1>*), align 64, !tbaa !1 20 tail call void @print_vecpred(i32 64, i8* bitcast (<16 x i32>* @Q6VecPredResult to i8*)) #3 21 ret i32 0 22} 23 24; Function Attrs: nounwind readnone 25declare <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #1 26 27; Function Attrs: nounwind readnone 28declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1 29 30declare void @print_vecpred(i32, i8*) #2 31 32attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } 33attributes #1 = { nounwind readnone } 34attributes #2 = { nounwind } 35 36!1 = !{!2, !2, i64 0} 37!2 = !{!"omnipotent char", !3, i64 0} 38!3 = !{!"Simple C/C++ TBAA"} 39