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1 /**************************************************************************
2 
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4                      VA Linux Systems Inc., Fremont, California.
5 
6 All Rights Reserved.
7 
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15 
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19 
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 
28 **************************************************************************/
29 
30 /*
31  * Authors:
32  *   Keith Whitwell <keithw@vmware.com>
33  */
34 
35 #include "main/glheader.h"
36 #include "main/mtypes.h"
37 #include "main/enums.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
40 
41 #include "math/m_xform.h"
42 
43 #include "swrast_setup/swrast_setup.h"
44 
45 #include "tnl/tnl.h"
46 #include "tnl/t_context.h"
47 #include "tnl/t_pipeline.h"
48 
49 #include "radeon_context.h"
50 #include "radeon_ioctl.h"
51 #include "radeon_state.h"
52 #include "radeon_swtcl.h"
53 #include "radeon_tcl.h"
54 #include "radeon_debug.h"
55 
56 
57 /* R100: xyzw, c0, c1/fog, stq[0..2]  = 4+1+1+3*3 = 15  right? */
58 /* R200: xyzw, c0, c1/fog, strq[0..5] = 4+1+1+4*6 = 30 */
59 #define RADEON_MAX_TNL_VERTEX_SIZE (15 * sizeof(GLfloat))	/* for mesa _tnl stage */
60 
61 /***********************************************************************
62  *                         Initialization
63  ***********************************************************************/
64 
65 #define EMIT_ATTR( ATTR, STYLE, F0 )					\
66 do {									\
67    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR);	\
68    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE);	\
69    rmesa->radeon.swtcl.vertex_attr_count++;					\
70    fmt_0 |= F0;								\
71 } while (0)
72 
73 #define EMIT_PAD( N )							\
74 do {									\
75    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0;		\
76    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD;	\
77    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N);		\
78    rmesa->radeon.swtcl.vertex_attr_count++;					\
79 } while (0)
80 
81 static GLuint radeon_cp_vc_frmts[3][2] =
82 {
83    { RADEON_CP_VC_FRMT_ST0, RADEON_CP_VC_FRMT_ST0 | RADEON_CP_VC_FRMT_Q0 },
84    { RADEON_CP_VC_FRMT_ST1, RADEON_CP_VC_FRMT_ST1 | RADEON_CP_VC_FRMT_Q1 },
85    { RADEON_CP_VC_FRMT_ST2, RADEON_CP_VC_FRMT_ST2 | RADEON_CP_VC_FRMT_Q2 },
86 };
87 
radeonSetVertexFormat(struct gl_context * ctx)88 static void radeonSetVertexFormat( struct gl_context *ctx )
89 {
90    r100ContextPtr rmesa = R100_CONTEXT( ctx );
91    TNLcontext *tnl = TNL_CONTEXT(ctx);
92    struct vertex_buffer *VB = &tnl->vb;
93    GLbitfield64 index_bitset = tnl->render_inputs_bitset;
94    int fmt_0 = 0;
95    int offset = 0;
96 
97    /* Important:
98     */
99    if ( VB->NdcPtr != NULL ) {
100       VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
101    }
102    else {
103       VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr;
104    }
105 
106    assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL );
107    rmesa->radeon.swtcl.vertex_attr_count = 0;
108 
109    /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
110     * build up a hardware vertex.
111     */
112    if ( !rmesa->swtcl.needproj ||
113         (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX))) {
114       /* for projtex */
115       EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F,
116 		 RADEON_CP_VC_FRMT_XY |	RADEON_CP_VC_FRMT_Z | RADEON_CP_VC_FRMT_W0 );
117       offset = 4;
118    }
119    else {
120       EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_3F,
121 		 RADEON_CP_VC_FRMT_XY |	RADEON_CP_VC_FRMT_Z );
122       offset = 3;
123    }
124 
125    rmesa->swtcl.coloroffset = offset;
126 #if MESA_LITTLE_ENDIAN
127    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA,
128 	      RADEON_CP_VC_FRMT_PKCOLOR );
129 #else
130    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR,
131 	      RADEON_CP_VC_FRMT_PKCOLOR );
132 #endif
133    offset += 1;
134 
135    rmesa->swtcl.specoffset = 0;
136    if (index_bitset &
137        (BITFIELD64_BIT(_TNL_ATTRIB_COLOR1) | BITFIELD64_BIT(_TNL_ATTRIB_FOG))) {
138 
139 #if MESA_LITTLE_ENDIAN
140       if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) {
141 	 rmesa->swtcl.specoffset = offset;
142 	 EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB,
143 	 	    RADEON_CP_VC_FRMT_PKSPEC );
144       }
145       else {
146 	 EMIT_PAD( 3 );
147       }
148 
149       if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) {
150 	 EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
151 	 	    RADEON_CP_VC_FRMT_PKSPEC );
152       }
153       else {
154 	 EMIT_PAD( 1 );
155       }
156 #else
157       if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) {
158 	 EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
159 	 	    RADEON_CP_VC_FRMT_PKSPEC );
160       }
161       else {
162 	 EMIT_PAD( 1 );
163       }
164 
165       if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) {
166 	 rmesa->swtcl.specoffset = offset;
167 	 EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR,
168 	 	    RADEON_CP_VC_FRMT_PKSPEC );
169       }
170       else {
171 	 EMIT_PAD( 3 );
172       }
173 #endif
174    }
175 
176    if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) {
177       int i;
178 
179       for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
180 	 if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_TEX(i))) {
181 	    GLuint sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size;
182 
183 	    switch (sz) {
184 	    case 1:
185 	    case 2:
186 	       EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F,
187 			  radeon_cp_vc_frmts[i][0] );
188 	       break;
189 	    case 3:
190 	       if (ctx->Texture.Unit[i]._Current &&
191                    ctx->Texture.Unit[i]._Current->Target == GL_TEXTURE_CUBE_MAP) {
192 	           EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
193 			      radeon_cp_vc_frmts[i][1] );
194                } else {
195 	           EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F,
196 			      radeon_cp_vc_frmts[i][0] );
197                }
198                break;
199 	    case 4:
200 	       if (ctx->Texture.Unit[i]._Current &&
201                    ctx->Texture.Unit[i]._Current->Target == GL_TEXTURE_CUBE_MAP) {
202 		  EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
203 			     radeon_cp_vc_frmts[i][1] );
204 	       } else {
205 		  EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F_XYW,
206 			     radeon_cp_vc_frmts[i][1] );
207 	       }
208 	       break;
209 	    default:
210 	       continue;
211 	    };
212 	 }
213       }
214    }
215 
216    if (rmesa->radeon.tnl_index_bitset != index_bitset ||
217        fmt_0 != rmesa->swtcl.vertex_format) {
218       RADEON_NEWPRIM(rmesa);
219       rmesa->swtcl.vertex_format = fmt_0;
220       rmesa->radeon.swtcl.vertex_size =
221 	  _tnl_install_attrs( ctx,
222 			      rmesa->radeon.swtcl.vertex_attrs,
223 			      rmesa->radeon.swtcl.vertex_attr_count,
224 			      NULL, 0 );
225       rmesa->radeon.swtcl.vertex_size /= 4;
226       rmesa->radeon.tnl_index_bitset = index_bitset;
227       radeon_print(RADEON_SWRENDER, RADEON_VERBOSE,
228 	  "%s: vertex_size= %d floats\n",  __func__, rmesa->radeon.swtcl.vertex_size);
229    }
230 }
231 
radeon_predict_emit_size(r100ContextPtr rmesa)232 static void radeon_predict_emit_size( r100ContextPtr rmesa )
233 {
234 
235     if (!rmesa->radeon.swtcl.emit_prediction) {
236         const int state_size = radeonCountStateEmitSize( &rmesa->radeon );
237         const int scissor_size = 8;
238         const int prims_size = 8;
239         const int vertex_size = 7;
240 
241         if (rcommonEnsureCmdBufSpace(&rmesa->radeon,
242                     state_size +
243                     (scissor_size + prims_size + vertex_size),
244                     __func__))
245             rmesa->radeon.swtcl.emit_prediction = radeonCountStateEmitSize( &rmesa->radeon );
246         else
247             rmesa->radeon.swtcl.emit_prediction = state_size;
248         rmesa->radeon.swtcl.emit_prediction += scissor_size + prims_size + vertex_size
249             + rmesa->radeon.cmdbuf.cs->cdw;
250     }
251 }
252 
radeonRenderStart(struct gl_context * ctx)253 static void radeonRenderStart( struct gl_context *ctx )
254 {
255     r100ContextPtr rmesa = R100_CONTEXT( ctx );
256 
257     radeonSetVertexFormat( ctx );
258 
259     if (rmesa->radeon.dma.flush != 0 &&
260             rmesa->radeon.dma.flush != rcommon_flush_last_swtcl_prim)
261         rmesa->radeon.dma.flush( ctx );
262 }
263 
264 
265 /**
266  * Set vertex state for SW TCL.  The primary purpose of this function is to
267  * determine in advance whether or not the hardware can / should do the
268  * projection divide or Mesa should do it.
269  */
radeonChooseVertexState(struct gl_context * ctx)270 void radeonChooseVertexState( struct gl_context *ctx )
271 {
272    r100ContextPtr rmesa = R100_CONTEXT( ctx );
273    TNLcontext *tnl = TNL_CONTEXT(ctx);
274 
275    GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
276    GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL ||
277                          ctx->Polygon.BackMode != GL_FILL);
278    GLboolean twosided = ctx->Light.Enabled && ctx->Light.Model.TwoSide;
279 
280    se_coord_fmt &= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
281 		     RADEON_VTX_Z_PRE_MULT_1_OVER_W0 |
282 		     RADEON_VTX_W0_IS_NOT_1_OVER_W0);
283 
284    /* We must ensure that we don't do _tnl_need_projected_coords while in a
285     * rasterization fallback.  As this function will be called again when we
286     * leave a rasterization fallback, we can just skip it for now.
287     */
288    if (rmesa->radeon.Fallback != 0)
289       return;
290 
291    /* HW perspective divide is a win, but tiny vertex formats are a
292     * bigger one.
293     */
294 
295    if ((0 == (tnl->render_inputs_bitset &
296         (BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)
297          | BITFIELD64_BIT(_TNL_ATTRIB_COLOR1))))
298        || twosided
299        || unfilled) {
300       rmesa->swtcl.needproj = GL_TRUE;
301       se_coord_fmt |= (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
302 		      RADEON_VTX_Z_PRE_MULT_1_OVER_W0);
303    }
304    else {
305       rmesa->swtcl.needproj = GL_FALSE;
306       se_coord_fmt |= (RADEON_VTX_W0_IS_NOT_1_OVER_W0);
307    }
308 
309    _tnl_need_projected_coords( ctx, rmesa->swtcl.needproj );
310 
311    if ( se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT] ) {
312       RADEON_STATECHANGE( rmesa, set );
313       rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
314    }
315 }
316 
r100_swtcl_flush(struct gl_context * ctx,uint32_t current_offset)317 void r100_swtcl_flush(struct gl_context *ctx, uint32_t current_offset)
318 {
319    r100ContextPtr rmesa = R100_CONTEXT(ctx);
320 
321 
322 
323    radeonEmitState(&rmesa->radeon);
324    radeonEmitVertexAOS( rmesa,
325 			rmesa->radeon.swtcl.vertex_size,
326 			rmesa->radeon.swtcl.bo,
327 			current_offset);
328 
329 
330    radeonEmitVbufPrim( rmesa,
331 		       rmesa->swtcl.vertex_format,
332 		       rmesa->radeon.swtcl.hw_primitive,
333 		       rmesa->radeon.swtcl.numverts);
334    if ( rmesa->radeon.swtcl.emit_prediction < rmesa->radeon.cmdbuf.cs->cdw )
335      WARN_ONCE("Rendering was %d commands larger than predicted size."
336 	 " We might overflow  command buffer.\n",
337 	 rmesa->radeon.cmdbuf.cs->cdw - rmesa->radeon.swtcl.emit_prediction );
338 
339 
340    rmesa->radeon.swtcl.emit_prediction = 0;
341 
342 }
343 
344 /*
345  * Render unclipped vertex buffers by emitting vertices directly to
346  * dma buffers.  Use strip/fan hardware primitives where possible.
347  * Try to simulate missing primitives with indexed vertices.
348  */
349 #define HAVE_POINTS      1
350 #define HAVE_LINES       1
351 #define HAVE_LINE_STRIPS 1
352 #define HAVE_TRIANGLES   1
353 #define HAVE_TRI_STRIPS  1
354 #define HAVE_TRI_FANS    1
355 #define HAVE_POLYGONS    0
356 /* \todo: is it possible to make "ELTS" work with t_vertex code ? */
357 #define HAVE_ELTS        0
358 
359 static const GLuint hw_prim[GL_POLYGON+1] = {
360    [GL_POINTS] = RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
361    [GL_LINES] = RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
362    [GL_LINE_LOOP] = 0,
363    [GL_LINE_STRIP] = RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP,
364    [GL_TRIANGLES] = RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
365    [GL_TRIANGLE_STRIP] = RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP,
366    [GL_TRIANGLE_FAN] = RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN,
367    [GL_QUADS] = 0,
368    [GL_QUAD_STRIP] = 0,
369    [GL_POLYGON] = 0
370 };
371 
372 static inline void
radeonDmaPrimitive(r100ContextPtr rmesa,GLenum prim)373 radeonDmaPrimitive( r100ContextPtr rmesa, GLenum prim )
374 {
375    RADEON_NEWPRIM( rmesa );
376    rmesa->radeon.swtcl.hw_primitive = hw_prim[prim];
377    //   assert(rmesa->radeon.dma.current.ptr == rmesa->radeon.dma.current.start);
378 }
379 
radeon_alloc_verts(r100ContextPtr rmesa,GLuint nr,GLuint size)380 static void* radeon_alloc_verts( r100ContextPtr rmesa , GLuint nr, GLuint size )
381 {
382    void *rv;
383    do {
384      radeon_predict_emit_size( rmesa );
385      rv = rcommonAllocDmaLowVerts( &rmesa->radeon, nr, size );
386    } while (!rv);
387    return rv;
388 }
389 
390 #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
391 #define INIT( prim ) radeonDmaPrimitive( rmesa, prim )
392 #define FLUSH()  RADEON_NEWPRIM( rmesa )
393 #define GET_CURRENT_VB_MAX_VERTS()					10\
394 //  (((int)rmesa->radeon.dma.current.end - (int)rmesa->radeon.dma.current.ptr) / (rmesa->radeon.swtcl.vertex_size*4))
395 #define GET_SUBSEQUENT_VB_MAX_VERTS() \
396   ((RADEON_BUFFER_SIZE) / (rmesa->radeon.swtcl.vertex_size*4))
397 #define ALLOC_VERTS( nr ) radeon_alloc_verts( rmesa, nr, rmesa->radeon.swtcl.vertex_size * 4 )
398 #define EMIT_VERTS( ctx, j, nr, buf ) \
399   _tnl_emit_vertices_to_buffer(ctx, j, (j)+(nr), buf)
400 
401 #define TAG(x) radeon_dma_##x
402 #include "tnl_dd/t_dd_dmatmp.h"
403 
404 
405 /**********************************************************************/
406 /*                          Render pipeline stage                     */
407 /**********************************************************************/
408 
409 
radeon_run_render(struct gl_context * ctx,struct tnl_pipeline_stage * stage)410 static GLboolean radeon_run_render( struct gl_context *ctx,
411 				    struct tnl_pipeline_stage *stage )
412 {
413    r100ContextPtr rmesa = R100_CONTEXT(ctx);
414    TNLcontext *tnl = TNL_CONTEXT(ctx);
415    struct vertex_buffer *VB = &tnl->vb;
416    const tnl_render_func *tab = TAG(render_tab_verts);
417    GLuint i;
418 
419    if (rmesa->radeon.swtcl.RenderIndex != 0 ||
420        !radeon_dma_validate_render( ctx, VB ))
421       return GL_TRUE;
422 
423    radeon_prepare_render(&rmesa->radeon);
424    if (rmesa->radeon.NewGLState)
425       radeonValidateState( ctx );
426 
427    tnl->Driver.Render.Start( ctx );
428 
429    for (i = 0 ; i < VB->PrimitiveCount ; i++)
430    {
431       GLuint prim = VB->Primitive[i].mode;
432       GLuint start = VB->Primitive[i].start;
433       GLuint length = VB->Primitive[i].count;
434 
435       if (!length)
436 	 continue;
437 
438       radeon_print(RADEON_SWRENDER, RADEON_NORMAL,
439 	  "radeon_render.c: prim %s %d..%d\n",
440 		 _mesa_enum_to_string(prim & PRIM_MODE_MASK),
441 		 start, start+length);
442 
443       if (length)
444          tab[prim & PRIM_MODE_MASK](ctx, start, length, prim);
445    }
446 
447    tnl->Driver.Render.Finish( ctx );
448 
449    return GL_FALSE;		/* finished the pipe */
450 }
451 
452 
453 
454 const struct tnl_pipeline_stage _radeon_render_stage =
455 {
456    "radeon render",
457    NULL,
458    NULL,
459    NULL,
460    NULL,
461    radeon_run_render		/* run */
462 };
463 
464 
465 /**************************************************************************/
466 
467 
468 static const GLuint reduced_hw_prim[GL_POLYGON+1] = {
469    [GL_POINTS] = RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
470    [GL_LINES] = RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
471    [GL_LINE_LOOP] = RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
472    [GL_LINE_STRIP] = RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
473    [GL_TRIANGLES] = RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
474    [GL_TRIANGLE_STRIP] = RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
475    [GL_TRIANGLE_FAN] = RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
476    [GL_QUADS] = RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
477    [GL_QUAD_STRIP] = RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
478    [GL_POLYGON] = RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
479 };
480 
481 static void radeonRasterPrimitive( struct gl_context *ctx, GLuint hwprim );
482 static void radeonRenderPrimitive( struct gl_context *ctx, GLenum prim );
483 static void radeonResetLineStipple( struct gl_context *ctx );
484 
485 
486 /***********************************************************************
487  *                    Emit primitives as inline vertices               *
488  ***********************************************************************/
489 
490 #undef LOCAL_VARS
491 #undef ALLOC_VERTS
492 #define CTX_ARG r100ContextPtr rmesa
493 #define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size
494 #define ALLOC_VERTS( n, size ) radeon_alloc_verts( rmesa, n, (size) * 4 )
495 #undef LOCAL_VARS
496 #define LOCAL_VARS						\
497    r100ContextPtr rmesa = R100_CONTEXT(ctx);		\
498    const char *radeonverts = (char *)rmesa->radeon.swtcl.verts;
499 #define VERT(x) (radeonVertex *)(radeonverts + ((x) * (vertsize) * sizeof(int)))
500 #define VERTEX radeonVertex
501 #undef TAG
502 #define TAG(x) radeon_##x
503 #include "tnl_dd/t_dd_triemit.h"
504 
505 
506 /***********************************************************************
507  *          Macros for t_dd_tritmp.h to draw basic primitives          *
508  ***********************************************************************/
509 
510 #define QUAD( a, b, c, d ) radeon_quad( rmesa, a, b, c, d )
511 #define TRI( a, b, c )     radeon_triangle( rmesa, a, b, c )
512 #define LINE( a, b )       radeon_line( rmesa, a, b )
513 #define POINT( a )         radeon_point( rmesa, a )
514 
515 /***********************************************************************
516  *              Build render functions from dd templates               *
517  ***********************************************************************/
518 
519 #define RADEON_TWOSIDE_BIT	0x01
520 #define RADEON_UNFILLED_BIT	0x02
521 #define RADEON_MAX_TRIFUNC	0x04
522 
523 
524 static struct {
525    tnl_points_func	        points;
526    tnl_line_func		line;
527    tnl_triangle_func	triangle;
528    tnl_quad_func		quad;
529 } rast_tab[RADEON_MAX_TRIFUNC];
530 
531 
532 #define DO_FALLBACK  0
533 #define DO_OFFSET    0
534 #define DO_UNFILLED ((IND & RADEON_UNFILLED_BIT) != 0)
535 #define DO_TWOSIDE  ((IND & RADEON_TWOSIDE_BIT) != 0)
536 #define DO_FLAT      0
537 #define DO_TRI       1
538 #define DO_QUAD      1
539 #define DO_LINE      1
540 #define DO_POINTS    1
541 #define DO_FULL_QUAD 1
542 
543 #define HAVE_SPEC   1
544 #define HAVE_BACK_COLORS  0
545 #define HAVE_HW_FLATSHADE 1
546 #define TAB rast_tab
547 
548 #define DEPTH_SCALE 1.0
549 #define UNFILLED_TRI unfilled_tri
550 #define UNFILLED_QUAD unfilled_quad
551 #define VERT_X(_v) _v->v.x
552 #define VERT_Y(_v) _v->v.y
553 #define VERT_Z(_v) _v->v.z
554 #define AREA_IS_CCW( a ) (a < 0)
555 #define GET_VERTEX(e) (rmesa->radeon.swtcl.verts + ((e) * rmesa->radeon.swtcl.vertex_size * sizeof(int)))
556 
557 #define VERT_SET_RGBA( v, c )  					\
558 do {								\
559    radeon_color_t *color = (radeon_color_t *)&((v)->ui[coloroffset]);	\
560    UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]);		\
561    UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]);		\
562    UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]);		\
563    UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]);		\
564 } while (0)
565 
566 #define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset]
567 
568 #define VERT_SET_SPEC( v, c )					\
569 do {								\
570    if (specoffset) {						\
571       radeon_color_t *spec = (radeon_color_t *)&((v)->ui[specoffset]);	\
572       UNCLAMPED_FLOAT_TO_UBYTE(spec->red, (c)[0]);	\
573       UNCLAMPED_FLOAT_TO_UBYTE(spec->green, (c)[1]);	\
574       UNCLAMPED_FLOAT_TO_UBYTE(spec->blue, (c)[2]);	\
575    }								\
576 } while (0)
577 #define VERT_COPY_SPEC( v0, v1 )			\
578 do {							\
579    if (specoffset) {					\
580       radeon_color_t *spec0 = (radeon_color_t *)&((v0)->ui[specoffset]);	\
581       radeon_color_t *spec1 = (radeon_color_t *)&((v1)->ui[specoffset]);	\
582       spec0->red   = spec1->red;	\
583       spec0->green = spec1->green;	\
584       spec0->blue  = spec1->blue; 	\
585    }							\
586 } while (0)
587 
588 /* These don't need LE32_TO_CPU() as they used to save and restore
589  * colors which are already in the correct format.
590  */
591 #define VERT_SAVE_RGBA( idx )    color[idx] = v[idx]->ui[coloroffset]
592 #define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx]
593 #define VERT_SAVE_SPEC( idx )    if (specoffset) spec[idx] = v[idx]->ui[specoffset]
594 #define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx]
595 
596 #undef LOCAL_VARS
597 #undef TAG
598 #undef INIT
599 
600 #define LOCAL_VARS(n)							\
601    r100ContextPtr rmesa = R100_CONTEXT(ctx);			\
602    GLuint color[n] = {0}, spec[n] = {0};						\
603    GLuint coloroffset = rmesa->swtcl.coloroffset;	\
604    GLuint specoffset = rmesa->swtcl.specoffset;			\
605    (void) color; (void) spec; (void) coloroffset; (void) specoffset;
606 
607 /***********************************************************************
608  *                Helpers for rendering unfilled primitives            *
609  ***********************************************************************/
610 
611 #define RASTERIZE(x) radeonRasterPrimitive( ctx, reduced_hw_prim[x] )
612 #define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive
613 #undef TAG
614 #define TAG(x) x
615 #include "tnl_dd/t_dd_unfilled.h"
616 #undef IND
617 
618 
619 /***********************************************************************
620  *                      Generate GL render functions                   *
621  ***********************************************************************/
622 
623 
624 #define IND (0)
625 #define TAG(x) x
626 #include "tnl_dd/t_dd_tritmp.h"
627 
628 #define IND (RADEON_TWOSIDE_BIT)
629 #define TAG(x) x##_twoside
630 #include "tnl_dd/t_dd_tritmp.h"
631 
632 #define IND (RADEON_UNFILLED_BIT)
633 #define TAG(x) x##_unfilled
634 #include "tnl_dd/t_dd_tritmp.h"
635 
636 #define IND (RADEON_TWOSIDE_BIT|RADEON_UNFILLED_BIT)
637 #define TAG(x) x##_twoside_unfilled
638 #include "tnl_dd/t_dd_tritmp.h"
639 
640 
init_rast_tab(void)641 static void init_rast_tab( void )
642 {
643    init();
644    init_twoside();
645    init_unfilled();
646    init_twoside_unfilled();
647 }
648 
649 /**********************************************************************/
650 /*               Render unclipped begin/end objects                   */
651 /**********************************************************************/
652 
653 #define RENDER_POINTS( start, count )		\
654    for ( ; start < count ; start++)		\
655       radeon_point( rmesa, VERT(start) )
656 #define RENDER_LINE( v0, v1 ) \
657    radeon_line( rmesa, VERT(v0), VERT(v1) )
658 #define RENDER_TRI( v0, v1, v2 )  \
659    radeon_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) )
660 #define RENDER_QUAD( v0, v1, v2, v3 ) \
661    radeon_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) )
662 #undef INIT
663 #define INIT(x) do {					\
664    radeonRenderPrimitive( ctx, x );			\
665 } while (0)
666 #undef LOCAL_VARS
667 #define LOCAL_VARS						\
668    r100ContextPtr rmesa = R100_CONTEXT(ctx);		\
669    const GLuint vertsize = rmesa->radeon.swtcl.vertex_size;		\
670    const char *radeonverts = (char *)rmesa->radeon.swtcl.verts;		\
671    const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts;	\
672    const GLboolean stipple = ctx->Line.StippleFlag;		\
673    (void) elt; (void) stipple;
674 #define RESET_STIPPLE	if ( stipple ) radeonResetLineStipple( ctx );
675 #define RESET_OCCLUSION
676 #define PRESERVE_VB_DEFS
677 #define ELT(x) (x)
678 #define TAG(x) radeon_##x##_verts
679 #include "tnl/t_vb_rendertmp.h"
680 #undef ELT
681 #undef TAG
682 #define TAG(x) radeon_##x##_elts
683 #define ELT(x) elt[x]
684 #include "tnl/t_vb_rendertmp.h"
685 
686 
687 
688 /**********************************************************************/
689 /*                    Choose render functions                         */
690 /**********************************************************************/
691 
radeonChooseRenderState(struct gl_context * ctx)692 void radeonChooseRenderState( struct gl_context *ctx )
693 {
694    TNLcontext *tnl = TNL_CONTEXT(ctx);
695    r100ContextPtr rmesa = R100_CONTEXT(ctx);
696    GLuint index = 0;
697    GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL ||
698                          ctx->Polygon.BackMode != GL_FILL);
699    GLboolean twosided = ctx->Light.Enabled && ctx->Light.Model.TwoSide;
700 
701    if (!rmesa->radeon.TclFallback || rmesa->radeon.Fallback)
702       return;
703 
704    if (twosided)
705       index |= RADEON_TWOSIDE_BIT;
706    if (unfilled)
707       index |= RADEON_UNFILLED_BIT;
708 
709    if (index != rmesa->radeon.swtcl.RenderIndex) {
710       tnl->Driver.Render.Points = rast_tab[index].points;
711       tnl->Driver.Render.Line = rast_tab[index].line;
712       tnl->Driver.Render.ClippedLine = rast_tab[index].line;
713       tnl->Driver.Render.Triangle = rast_tab[index].triangle;
714       tnl->Driver.Render.Quad = rast_tab[index].quad;
715 
716       if (index == 0) {
717 	 tnl->Driver.Render.PrimTabVerts = radeon_render_tab_verts;
718 	 tnl->Driver.Render.PrimTabElts = radeon_render_tab_elts;
719 	 tnl->Driver.Render.ClippedPolygon = radeon_fast_clipped_poly;
720       } else {
721 	 tnl->Driver.Render.PrimTabVerts = _tnl_render_tab_verts;
722 	 tnl->Driver.Render.PrimTabElts = _tnl_render_tab_elts;
723 	 tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon;
724       }
725 
726       rmesa->radeon.swtcl.RenderIndex = index;
727    }
728 }
729 
730 
731 /**********************************************************************/
732 /*                 High level hooks for t_vb_render.c                 */
733 /**********************************************************************/
734 
735 
radeonRasterPrimitive(struct gl_context * ctx,GLuint hwprim)736 static void radeonRasterPrimitive( struct gl_context *ctx, GLuint hwprim )
737 {
738    r100ContextPtr rmesa = R100_CONTEXT(ctx);
739 
740    if (rmesa->radeon.swtcl.hw_primitive != hwprim) {
741       RADEON_NEWPRIM( rmesa );
742       rmesa->radeon.swtcl.hw_primitive = hwprim;
743    }
744 }
745 
radeonRenderPrimitive(struct gl_context * ctx,GLenum prim)746 static void radeonRenderPrimitive( struct gl_context *ctx, GLenum prim )
747 {
748    r100ContextPtr rmesa = R100_CONTEXT(ctx);
749    GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL ||
750                          ctx->Polygon.BackMode != GL_FILL);
751 
752    rmesa->radeon.swtcl.render_primitive = prim;
753    if (prim < GL_TRIANGLES || !unfilled)
754       radeonRasterPrimitive( ctx, reduced_hw_prim[prim] );
755 }
756 
radeonRenderFinish(struct gl_context * ctx)757 static void radeonRenderFinish( struct gl_context *ctx )
758 {
759 }
760 
radeonResetLineStipple(struct gl_context * ctx)761 static void radeonResetLineStipple( struct gl_context *ctx )
762 {
763    r100ContextPtr rmesa = R100_CONTEXT(ctx);
764    RADEON_STATECHANGE( rmesa, lin );
765 }
766 
767 
768 /**********************************************************************/
769 /*           Transition to/from hardware rasterization.               */
770 /**********************************************************************/
771 
772 static const char * const fallbackStrings[] = {
773    "Texture mode",
774    "glDrawBuffer(GL_FRONT_AND_BACK)",
775    "glEnable(GL_STENCIL) without hw stencil buffer",
776    "glRenderMode(selection or feedback)",
777    "glBlendEquation",
778    "glBlendFunc",
779    "RADEON_NO_RAST",
780    "Mixing GL_CLAMP_TO_BORDER and GL_CLAMP (or GL_MIRROR_CLAMP_ATI)"
781 };
782 
783 
getFallbackString(GLuint bit)784 static const char *getFallbackString(GLuint bit)
785 {
786    int i = 0;
787    while (bit > 1) {
788       i++;
789       bit >>= 1;
790    }
791    return fallbackStrings[i];
792 }
793 
794 
radeonFallback(struct gl_context * ctx,GLuint bit,GLboolean mode)795 void radeonFallback( struct gl_context *ctx, GLuint bit, GLboolean mode )
796 {
797    r100ContextPtr rmesa = R100_CONTEXT(ctx);
798    TNLcontext *tnl = TNL_CONTEXT(ctx);
799    GLuint oldfallback = rmesa->radeon.Fallback;
800 
801    if (mode) {
802       rmesa->radeon.Fallback |= bit;
803       if (oldfallback == 0) {
804 	 radeon_firevertices(&rmesa->radeon);
805 	 TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_TRUE );
806 	 _swsetup_Wakeup( ctx );
807 	 rmesa->radeon.swtcl.RenderIndex = ~0;
808          if (RADEON_DEBUG & RADEON_FALLBACKS) {
809             fprintf(stderr, "Radeon begin rasterization fallback: 0x%x %s\n",
810                     bit, getFallbackString(bit));
811          }
812       }
813    }
814    else {
815       rmesa->radeon.Fallback &= ~bit;
816       if (oldfallback == bit) {
817 	 _swrast_flush( ctx );
818 	 tnl->Driver.Render.Start = radeonRenderStart;
819 	 tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
820 	 tnl->Driver.Render.Finish = radeonRenderFinish;
821 
822 	 tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
823 	 tnl->Driver.Render.CopyPV = _tnl_copy_pv;
824 	 tnl->Driver.Render.Interp = _tnl_interp;
825 
826 	 tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
827 	 TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_FALSE );
828 	 if (rmesa->radeon.TclFallback) {
829 	    /* These are already done if rmesa->radeon.TclFallback goes to
830 	     * zero above. But not if it doesn't (RADEON_NO_TCL for
831 	     * example?)
832 	     */
833 	    _tnl_invalidate_vertex_state( ctx, ~0 );
834 	    _tnl_invalidate_vertices( ctx, ~0 );
835 	    rmesa->radeon.tnl_index_bitset = 0;
836 	    radeonChooseVertexState( ctx );
837 	    radeonChooseRenderState( ctx );
838 	 }
839          if (RADEON_DEBUG & RADEON_FALLBACKS) {
840             fprintf(stderr, "Radeon end rasterization fallback: 0x%x %s\n",
841                     bit, getFallbackString(bit));
842          }
843       }
844    }
845 }
846 
847 
848 /**********************************************************************/
849 /*                            Initialization.                         */
850 /**********************************************************************/
851 
radeonInitSwtcl(struct gl_context * ctx)852 void radeonInitSwtcl( struct gl_context *ctx )
853 {
854    TNLcontext *tnl = TNL_CONTEXT(ctx);
855    r100ContextPtr rmesa = R100_CONTEXT(ctx);
856    static int firsttime = 1;
857 
858    if (firsttime) {
859       init_rast_tab();
860       firsttime = 0;
861    }
862    rmesa->radeon.swtcl.emit_prediction = 0;
863 
864    tnl->Driver.Render.Start = radeonRenderStart;
865    tnl->Driver.Render.Finish = radeonRenderFinish;
866    tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
867    tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
868    tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
869    tnl->Driver.Render.CopyPV = _tnl_copy_pv;
870    tnl->Driver.Render.Interp = _tnl_interp;
871 
872    _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12,
873 		       RADEON_MAX_TNL_VERTEX_SIZE);
874 
875    rmesa->radeon.swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf;
876    rmesa->radeon.swtcl.RenderIndex = ~0;
877    rmesa->radeon.swtcl.render_primitive = GL_TRIANGLES;
878    rmesa->radeon.swtcl.hw_primitive = 0;
879 }
880 
881