1 // Copyright 2014 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef V8_COMPILER_REGISTER_CONFIGURATION_H_ 6 #define V8_COMPILER_REGISTER_CONFIGURATION_H_ 7 8 #include "src/base/macros.h" 9 #include "src/globals.h" 10 #include "src/machine-type.h" 11 12 namespace v8 { 13 namespace internal { 14 15 // An architecture independent representation of the sets of registers available 16 // for instruction creation. 17 class V8_EXPORT_PRIVATE RegisterConfiguration { 18 public: 19 enum AliasingKind { 20 // Registers alias a single register of every other size (e.g. Intel). 21 OVERLAP, 22 // Registers alias two registers of the next smaller size (e.g. ARM). 23 COMBINE 24 }; 25 26 // Architecture independent maxes. 27 static const int kMaxGeneralRegisters = 32; 28 static const int kMaxFPRegisters = 32; 29 30 // Default RegisterConfigurations for the target architecture. 31 // TODO(X87): This distinction in RegisterConfigurations is temporary 32 // until x87 TF supports all of the registers that Crankshaft does. 33 static const RegisterConfiguration* Crankshaft(); 34 static const RegisterConfiguration* Turbofan(); 35 36 RegisterConfiguration(int num_general_registers, int num_double_registers, 37 int num_allocatable_general_registers, 38 int num_allocatable_double_registers, 39 const int* allocatable_general_codes, 40 const int* allocatable_double_codes, 41 AliasingKind fp_aliasing_kind, 42 char const* const* general_names, 43 char const* const* float_names, 44 char const* const* double_names, 45 char const* const* simd128_names); 46 num_general_registers()47 int num_general_registers() const { return num_general_registers_; } num_float_registers()48 int num_float_registers() const { return num_float_registers_; } num_double_registers()49 int num_double_registers() const { return num_double_registers_; } num_simd128_registers()50 int num_simd128_registers() const { return num_simd128_registers_; } num_allocatable_general_registers()51 int num_allocatable_general_registers() const { 52 return num_allocatable_general_registers_; 53 } num_allocatable_float_registers()54 int num_allocatable_float_registers() const { 55 return num_allocatable_float_registers_; 56 } num_allocatable_double_registers()57 int num_allocatable_double_registers() const { 58 return num_allocatable_double_registers_; 59 } num_allocatable_simd128_registers()60 int num_allocatable_simd128_registers() const { 61 return num_allocatable_simd128_registers_; 62 } fp_aliasing_kind()63 AliasingKind fp_aliasing_kind() const { return fp_aliasing_kind_; } allocatable_general_codes_mask()64 int32_t allocatable_general_codes_mask() const { 65 return allocatable_general_codes_mask_; 66 } allocatable_double_codes_mask()67 int32_t allocatable_double_codes_mask() const { 68 return allocatable_double_codes_mask_; 69 } GetAllocatableGeneralCode(int index)70 int GetAllocatableGeneralCode(int index) const { 71 return allocatable_general_codes_[index]; 72 } IsAllocatableGeneralCode(int index)73 bool IsAllocatableGeneralCode(int index) const { 74 return ((1 << index) & allocatable_general_codes_mask_) != 0; 75 } GetAllocatableFloatCode(int index)76 int GetAllocatableFloatCode(int index) const { 77 return allocatable_float_codes_[index]; 78 } IsAllocatableFloatCode(int index)79 bool IsAllocatableFloatCode(int index) const { 80 return ((1 << index) & allocatable_float_codes_mask_) != 0; 81 } GetAllocatableDoubleCode(int index)82 int GetAllocatableDoubleCode(int index) const { 83 return allocatable_double_codes_[index]; 84 } IsAllocatableDoubleCode(int index)85 bool IsAllocatableDoubleCode(int index) const { 86 return ((1 << index) & allocatable_double_codes_mask_) != 0; 87 } GetAllocatableSimd128Code(int index)88 int GetAllocatableSimd128Code(int index) const { 89 return allocatable_simd128_codes_[index]; 90 } IsAllocatableSimd128Code(int index)91 bool IsAllocatableSimd128Code(int index) const { 92 return ((1 << index) & allocatable_simd128_codes_mask_) != 0; 93 } GetGeneralRegisterName(int code)94 const char* GetGeneralRegisterName(int code) const { 95 return general_register_names_[code]; 96 } GetFloatRegisterName(int code)97 const char* GetFloatRegisterName(int code) const { 98 return float_register_names_[code]; 99 } GetDoubleRegisterName(int code)100 const char* GetDoubleRegisterName(int code) const { 101 return double_register_names_[code]; 102 } GetSimd128RegisterName(int code)103 const char* GetSimd128RegisterName(int code) const { 104 return simd128_register_names_[code]; 105 } allocatable_general_codes()106 const int* allocatable_general_codes() const { 107 return allocatable_general_codes_; 108 } allocatable_float_codes()109 const int* allocatable_float_codes() const { 110 return allocatable_float_codes_; 111 } allocatable_double_codes()112 const int* allocatable_double_codes() const { 113 return allocatable_double_codes_; 114 } allocatable_simd128_codes()115 const int* allocatable_simd128_codes() const { 116 return allocatable_simd128_codes_; 117 } 118 119 // Aliasing calculations for floating point registers, when fp_aliasing_kind() 120 // is COMBINE. Currently only implemented for kFloat32, kFloat64, or kSimd128 121 // reps. Returns the number of aliases, and if > 0, alias_base_index is set to 122 // the index of the first alias. 123 int GetAliases(MachineRepresentation rep, int index, 124 MachineRepresentation other_rep, int* alias_base_index) const; 125 // Returns a value indicating whether two registers alias each other, when 126 // fp_aliasing_kind() is COMBINE. Currently implemented for kFloat32, 127 // kFloat64, or kSimd128 reps. 128 bool AreAliases(MachineRepresentation rep, int index, 129 MachineRepresentation other_rep, int other_index) const; 130 131 private: 132 const int num_general_registers_; 133 int num_float_registers_; 134 const int num_double_registers_; 135 int num_simd128_registers_; 136 int num_allocatable_general_registers_; 137 int num_allocatable_float_registers_; 138 int num_allocatable_double_registers_; 139 int num_allocatable_simd128_registers_; 140 int32_t allocatable_general_codes_mask_; 141 int32_t allocatable_float_codes_mask_; 142 int32_t allocatable_double_codes_mask_; 143 int32_t allocatable_simd128_codes_mask_; 144 const int* allocatable_general_codes_; 145 int allocatable_float_codes_[kMaxFPRegisters]; 146 const int* allocatable_double_codes_; 147 int allocatable_simd128_codes_[kMaxFPRegisters]; 148 AliasingKind fp_aliasing_kind_; 149 char const* const* general_register_names_; 150 char const* const* float_register_names_; 151 char const* const* double_register_names_; 152 char const* const* simd128_register_names_; 153 }; 154 155 } // namespace internal 156 } // namespace v8 157 158 #endif // V8_COMPILER_REGISTER_CONFIGURATION_H_ 159