1 2This file records register use conventions and info for the 4 3supported platforms (since it is ABI dependent). This is so as to 4avoid having to endlessly re-look up this info in ABI documents. 5 6 ----------------------- 7 8x86-linux 9~~~~~~~~~ 10 11Reg Callee Arg 12Name Saves? Reg? Comment Vex-uses? 13-------------------------------------------------------------- 14eax n n int[31:0] retreg y 15ebx y n y 16ecx n n y 17edx n n int[63:32] retreg y 18esi y n y 19edi y n y 20ebp y n & guest state 21esp reserved n/a n/a 22eflags n n/a y 23st0 n ? n fp retreg y 24st1-7 n ? n y 25xmm0-7 n ? n y 26gs Thread ptr 27 28In the case where arguments are passed in registers, the arg1,2,3 29registers are EAX, EDX, and ECX respectively. 30 31amd64-linux 32~~~~~~~~~~~ 33 34Reg Callee Arg 35Name Saves? Reg? Comment Vex-uses? 36------------------------------------------------------------------- 37rax n n int[63:0] retreg 38rbx y n y 39rcx n int#4 40rdx n int#3 int[127:64] retreg 41rsi n int#2 y 42rdi n int#1 y 43rbp y n & guest state 44rsp reserved n/a n/a 45r8 n int#5 y 46r9 n int#6 y 47r10 n ? 48r11 n jmp temporary 49r12-15 y y 50eflags n n/a y 51st0-7 n n long double retreg y 52xmm0 n fp#1 fp retreg 53xmm1 n fp#2 fp-high retreg 54xmm2-7 n fp#3-8 y (3-7) 55xmm8-15 n y (8-12) 56fs thread ptr 57 58ppc32-linux 59~~~~~~~~~~~ 60 61Reg Callee Arg 62Name Saves? Reg? Comment Vex-uses? 63------------------------------------------------------------------- 64r0 n n sometimes RAZ 65r1 y n stack pointer 66r2 n n thread ptr 67r3 n int#1 int[31:0] retreg y 68r4 n int#2 also int retreg y 69r5 n int#3 y 70r6 n int#4 y 71r7 n int#5 y 72r8 n int#6 y 73r9 n int#7 y 74r10 n int#8 y 75r11 n y 76r12 n y 77r13 ? 78r14-28 y y 79r29 y reserved for dispatcher 80r30 y altivec spill temporary 81r31 y & guest state 82f0 n 83f1 n fp#1 fp retreg 84f2-8 n fp#2-8 85f9-13 n 86f14-31 y y (14-21) 87v0-v19 ? 88v20-31 y y (20-27,29) 89cr0-7 90lr y return address 91ctr n 92xer n 93fpscr 94 95 96ppc64-linux 97~~~~~~~~~~~ 98Reg Callee Arg 99Name Saves? Reg? Comment Vex-uses? 100------------------------------------------------------------------- 101r13 n n thread ptr 102TBD 103 104 105arm-linux 106~~~~~~~~~ 107 108Reg Callee Arg 109Name Saves? Reg? Comment Vex-uses? 110-------------------------------------------------------------- 111r0 int#1 int[31:0] retreg? avail 112r1 int#2 int[63:32] retreg? avail 113r2 int#3 avail 114r3 int#4 avail 115r4 y avail 116r5 y avail 117r6 y avail 118r7 y avail 119r8 y GSP 120r9 y (but only on Linux; not in general) avail 121r10 y avail 122r11 y avail 123r12 possibly used by linker? unavail 124r13(sp) unavail 125r14(lr) unavail 126r15(pc) unavail 127cp15/c3/r2 thread ptr (see libvex_guest_arm.h, guest_TPIDRURO) 128 129VFP: d8-d15 are callee-saved 130r12 (IP) is probably available for use as a caller-saved 131register; but instead we use it as an intermediate for 132holding the address for F32/F64 spills, since the VFP load/store 133insns have reg+offset forms for offsets only up to 1020, which 134often isn't enough. 135 136 137arm64-linux 138~~~~~~~~~~~ 139 140Reg Callee Arg 141Name Saves? Reg? Comment Vex-uses? 142--------------------------------------------------------------- 143r0 int#0 ret#0 (??) 144r1 int#1 ret#1 (??) 145r2-7 int#2..7 146r8 "Indirect res loc reg" ProfInc scratch 147r9 "Temporary regs" chaining scratch 148r10-15 "Temporary regs" avail 149r16(IP0) 150r17(IP1) 151r18 "Platform reg" 152r19-20 "Temporary regs" 153r21 y "Callee saved" GSP 154r22-28 y "Callee saved" 155r29(FP) y 156r30(LR) y 157 158NZCV "Status register" 159 160Is there a TLS register? 161 162x21 is the GSP. x9 is a scratch chaining/spill temp. Neither 163are available to the register allocator. 164 165Q registers: 166It's a little awkward. Basically, D registers are the same as ARM, 167so d0-d7 and d16-d31 are caller-saved, but d8-d15 are callee-saved. 168 169Q registers are the same, except that the upper 64 bits of q8-q15 170are caller-saved. 171 172The idea is that you only need to preserve D registers, not Q 173registers. 174 175 176 177s390x-linux 178~~~~~~~~~~~ 179 180Reg Callee Arg 181Name Saves? Reg? Comment Vex-uses? 182-------------------------------------------------------------- 183r0 n see below unavail 184r1 n avail 185r2 n int#1 return value avail 186r3 n int#2 avail 187r4 n int#3 avail 188r5 n int#4 avail 189r6 y int#5 avail 190r7 y avail 191r8 y avail 192r9 y avail 193r10 y see below avail 194r11 y see below avail 195r12 y unavail VG_(dispatch_ctr) 196r13 y unavail gsp 197r14(lr) n unavail lr 198r15(sp) y unavail sp 199 200f0 n return value avail 201f1-f7 n avail 202f8-f11 y avail 203f12-f15 y see below avail 204a0 n thread ptr high word 205a1 n thread ptr low word 206 207When r0 is used as a base or index register its contents is 208ignored and the value 0 is used instead. This is the reason 209why VEX cannot use it. 210 211r10, r11 as well as f12-f15 are used as real regs during insn 212selection when register pairs are required. 213 214ppc32-aix5 215~~~~~~~~~~ 216 217Reg Callee Arg 218Name Saves? Reg? Comment Vex-uses? 219------------------------------------------------------------------- 220r0 n n sometimes RAZ 221r1 y n stack pointer 222r2 n n TOC pointer 223r3 n int#1 int[31:0] retreg y 224r4 n int#2 also int retreg y 225r5 n int#3 y 226r6 n int#4 y 227r7 n int#5 y 228r8 n int#6 y 229r9 n int#7 y 230r10 n int#8 y 231r11 n "env pointer?!" y 232r12 n "exn handling" y 233r13 ? "reserved in 64-bit env" 234r14-28 y y 235r29 y reserved for dispatcher 236r30 y altivec spill temporary 237r31 y & guest state 238f0 n 239f1 n fp#1 fp retreg 240f2-13 n fp#2-13 241f14-31 y y (14-21) 242v0-v19 ? 243v20-31 y y (20-27,29) 244cr0-7 245lr y return address 246ctr n 247xer n 248fpscr 249 250