Lines Matching refs:DCI
4562 const AArch64TargetLowering::DAGCombinerInfo &DCI, unsigned Opcode, in getEstimate() argument
4574 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals; in getEstimate()
4579 return DCI.DAG.getNode(Opcode, SDLoc(Operand), VT, Operand); in getEstimate()
4583 DAGCombinerInfo &DCI, unsigned &ExtraSteps) const { in getRecipEstimate() argument
4584 return getEstimate(*Subtarget, DCI, AArch64ISD::FRECPE, Operand, ExtraSteps); in getRecipEstimate()
4588 DAGCombinerInfo &DCI, unsigned &ExtraSteps, bool &UseOneConst) const { in getRsqrtEstimate() argument
4590 return getEstimate(*Subtarget, DCI, AArch64ISD::FRSQRTE, Operand, ExtraSteps); in getRsqrtEstimate()
7481 TargetLowering::DAGCombinerInfo &DCI, in performXorCombine() argument
7483 if (DCI.isBeforeLegalizeOps()) in performXorCombine()
7539 TargetLowering::DAGCombinerInfo &DCI, in performMulCombine() argument
7541 if (DCI.isBeforeLegalizeOps()) in performMulCombine()
7686 TargetLowering::DAGCombinerInfo &DCI, in performFpToIntCombine() argument
7734 if (ResTy == MVT::v4i64 && DCI.isBeforeLegalizeOps()) in performFpToIntCombine()
7737 assert((ResTy != MVT::v4i64 || DCI.isBeforeLegalizeOps()) && in performFpToIntCombine()
7844 TargetLowering::DAGCombinerInfo &DCI) { in tryCombineToEXTR() argument
7845 SelectionDAG &DAG = DCI.DAG; in tryCombineToEXTR()
7884 TargetLowering::DAGCombinerInfo &DCI) { in tryCombineToBSL() argument
7886 SelectionDAG &DAG = DCI.DAG; in tryCombineToBSL()
7930 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, in performORCombine() argument
7933 SelectionDAG &DAG = DCI.DAG; in performORCombine()
7939 if (SDValue Res = tryCombineToEXTR(N, DCI)) in performORCombine()
7942 if (SDValue Res = tryCombineToBSL(N, DCI)) in performORCombine()
7949 TargetLowering::DAGCombinerInfo &DCI) { in performSRLCombine() argument
7950 SelectionDAG &DAG = DCI.DAG; in performSRLCombine()
7977 TargetLowering::DAGCombinerInfo &DCI, in performBitcastCombine() argument
7981 if (DCI.isBeforeLegalizeOps()) in performBitcastCombine()
8043 TargetLowering::DAGCombinerInfo &DCI, in performConcatVectorsCombine() argument
8084 if (DCI.isBeforeLegalizeOps()) in performConcatVectorsCombine()
8124 TargetLowering::DAGCombinerInfo &DCI, in tryCombineFixedPointConvert() argument
8128 if (DCI.isBeforeLegalizeOps()) in tryCombineFixedPointConvert()
8368 TargetLowering::DAGCombinerInfo &DCI, in performAddSubLongCombine() argument
8370 if (DCI.isBeforeLegalizeOps()) in performAddSubLongCombine()
8417 TargetLowering::DAGCombinerInfo &DCI, in tryCombineLongOpWithDup() argument
8419 if (DCI.isBeforeLegalizeOps()) in tryCombineLongOpWithDup()
8532 TargetLowering::DAGCombinerInfo &DCI, in performIntrinsicCombine() argument
8534 SelectionDAG &DAG = DCI.DAG; in performIntrinsicCombine()
8541 return tryCombineFixedPointConvert(N, DCI, DAG); in performIntrinsicCombine()
8570 return tryCombineLongOpWithDup(IID, N, DCI, DAG); in performIntrinsicCombine()
8588 TargetLowering::DAGCombinerInfo &DCI, in performExtendCombine() argument
8594 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND && in performExtendCombine()
8600 SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG); in performExtendCombine()
8633 if (!DCI.isBeforeLegalizeOps()) in performExtendCombine()
8745 static SDValue split16BStores(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, in split16BStores() argument
8748 if (!DCI.isBeforeLegalize()) in split16BStores()
8812 TargetLowering::DAGCombinerInfo &DCI, in performPostLD1Combine() argument
8814 if (DCI.isBeforeLegalizeOps()) in performPostLD1Combine()
8817 SelectionDAG &DAG = DCI.DAG; in performPostLD1Combine()
8899 DCI.CombineTo(LD, NewResults); in performPostLD1Combine()
8900 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result in performPostLD1Combine()
8901 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register in performPostLD1Combine()
8911 TargetLowering::DAGCombinerInfo &DCI, in performTBISimplification() argument
8915 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(), in performTBISimplification()
8916 DCI.isBeforeLegalizeOps()); in performTBISimplification()
8919 DCI.CommitTargetLoweringOpt(TLO); in performTBISimplification()
8926 TargetLowering::DAGCombinerInfo &DCI, in performSTORECombine() argument
8929 if (SDValue Split = split16BStores(N, DCI, DAG, Subtarget)) in performSTORECombine()
8933 performTBISimplification(N->getOperand(2), DCI, DAG)) in performSTORECombine()
9203 TargetLowering::DAGCombinerInfo &DCI, in performNEONPostLDSTCombine() argument
9205 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in performNEONPostLDSTCombine()
9324 DCI.CombineTo(N, NewResults); in performNEONPostLDSTCombine()
9325 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs)); in performNEONPostLDSTCombine()
9516 TargetLowering::DAGCombinerInfo &DCI, in performCONDCombine() argument
9590 TargetLowering::DAGCombinerInfo &DCI, in performBRCONDCombine() argument
9592 if (SDValue NV = performCONDCombine(N, DCI, DAG, 2, 3)) in performBRCONDCombine()
9639 DCI.CombineTo(N, BR, false); in performBRCONDCombine()
9716 TargetLowering::DAGCombinerInfo &DCI, in performTBZCombine() argument
9776 TargetLowering::DAGCombinerInfo &DCI) { in performSelectCombine() argument
9777 SelectionDAG &DAG = DCI.DAG; in performSelectCombine()
9814 assert(DCI.isBeforeLegalize() || in performSelectCombine()
9844 DAGCombinerInfo &DCI) const { in PerformDAGCombine()
9845 SelectionDAG &DAG = DCI.DAG; in PerformDAGCombine()
9851 return performAddSubLongCombine(N, DCI, DAG); in PerformDAGCombine()
9853 return performXorCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
9855 return performMulCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
9861 return performFpToIntCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
9865 return performORCombine(N, DCI, Subtarget); in PerformDAGCombine()
9867 return performSRLCombine(N, DCI); in PerformDAGCombine()
9869 return performIntrinsicCombine(N, DCI, Subtarget); in PerformDAGCombine()
9873 return performExtendCombine(N, DCI, DAG); in PerformDAGCombine()
9875 return performBitcastCombine(N, DCI, DAG); in PerformDAGCombine()
9877 return performConcatVectorsCombine(N, DCI, DAG); in PerformDAGCombine()
9879 SDValue RV = performSelectCombine(N, DCI); in PerformDAGCombine()
9885 return performVSelectCombine(N, DCI.DAG); in PerformDAGCombine()
9887 if (performTBISimplification(N->getOperand(1), DCI, DAG)) in PerformDAGCombine()
9891 return performSTORECombine(N, DCI, DAG, Subtarget); in PerformDAGCombine()
9893 return performBRCONDCombine(N, DCI, DAG); in PerformDAGCombine()
9896 return performTBZCombine(N, DCI, DAG); in PerformDAGCombine()
9898 return performCONDCombine(N, DCI, DAG, 2, 3); in PerformDAGCombine()
9900 return performPostLD1Combine(N, DCI, false); in PerformDAGCombine()
9904 return performPostLD1Combine(N, DCI, true); in PerformDAGCombine()
9931 return performNEONPostLDSTCombine(N, DCI, DAG); in PerformDAGCombine()