Lines Matching refs:opc
879 class CRmSystemI<Operand crmtype, bits<3> opc, string asm,
886 let Inst{7-5} = opc;
1045 // case opc of
1052 class BaseBranchReg<bits<4> opc, dag oops, dag iops, string asm,
1056 let Inst{24-21} = opc;
1062 class BranchReg<bits<4> opc, string asm, list<dag> pattern>
1063 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> {
1069 class SpecialReturn<bits<4> opc, string asm>
1070 : BaseBranchReg<opc, (outs), (ins), asm, "", []> {
1270 class BaseOneOperandData<bits<3> opc, RegisterClass regtype, string asm,
1279 let Inst{12-10} = opc;
1285 multiclass OneOperandData<bits<3> opc, string asm,
1287 def Wr : BaseOneOperandData<opc, GPR32, asm, node> {
1291 def Xr : BaseOneOperandData<opc, GPR64, asm, node> {
1296 class OneWRegData<bits<3> opc, string asm, SDPatternOperator node>
1297 : BaseOneOperandData<opc, GPR32, asm, node> {
1301 class OneXRegData<bits<3> opc, string asm, SDPatternOperator node>
1302 : BaseOneOperandData<opc, GPR64, asm, node> {
1363 class BaseTwoOperand<bits<4> opc, RegisterClass regtype, string asm,
1374 let Inst{13-10} = opc;
1430 class BaseMulAccum<bit isSub, bits<3> opc, RegisterClass multype,
1440 let Inst{23-21} = opc;
1463 class WideMulAccum<bit isSub, bits<3> opc, string asm,
1465 : BaseMulAccum<isSub, opc, GPR32, GPR64, asm,
1472 class MulHi<bits<3> opc, string asm, SDNode OpNode>
1481 let Inst{23-21} = opc;
1561 class BaseMoveImmediate<bits<2> opc, RegisterClass regtype, Operand shifter,
1569 let Inst{30-29} = opc;
1578 multiclass MoveImmediate<bits<2> opc, string asm> {
1579 def Wi : BaseMoveImmediate<opc, GPR32, movimm32_shift, asm> {
1583 def Xi : BaseMoveImmediate<opc, GPR64, movimm64_shift, asm> {
1589 class BaseInsertImmediate<bits<2> opc, RegisterClass regtype, Operand shifter,
1598 let Inst{30-29} = opc;
1607 multiclass InsertImmediate<bits<2> opc, string asm> {
1608 def Wi : BaseInsertImmediate<opc, GPR32, movimm32_shift, asm> {
1612 def Xi : BaseInsertImmediate<opc, GPR64, movimm64_shift, asm> {
1964 class BaseBitfieldImm<bits<2> opc,
1974 let Inst{30-29} = opc;
1982 multiclass BitfieldImm<bits<2> opc, string asm> {
1983 def Wri : BaseBitfieldImm<opc, GPR32, imm0_31, asm> {
1990 def Xri : BaseBitfieldImm<opc, GPR64, imm0_63, asm> {
1997 class BaseBitfieldImmWith2RegArgs<bits<2> opc,
2008 let Inst{30-29} = opc;
2016 multiclass BitfieldImmWith2RegArgs<bits<2> opc, string asm> {
2017 def Wri : BaseBitfieldImmWith2RegArgs<opc, GPR32, imm0_31, asm> {
2024 def Xri : BaseBitfieldImmWith2RegArgs<opc, GPR64, imm0_63, asm> {
2035 class BaseLogicalImm<bits<2> opc, RegisterClass dregtype,
2044 let Inst{30-29} = opc;
2056 class BaseLogicalSReg<bits<2> opc, bit N, RegisterClass regtype,
2070 let Inst{30-29} = opc;
2087 multiclass LogicalImm<bits<2> opc, string mnemonic, SDNode OpNode,
2090 def Wri : BaseLogicalImm<opc, GPR32sp, GPR32, logical_imm32, mnemonic,
2097 def Xri : BaseLogicalImm<opc, GPR64sp, GPR64, logical_imm64, mnemonic,
2111 multiclass LogicalImmS<bits<2> opc, string mnemonic, SDNode OpNode,
2114 def Wri : BaseLogicalImm<opc, GPR32, GPR32, logical_imm32, mnemonic,
2119 def Xri : BaseLogicalImm<opc, GPR64, GPR64, logical_imm64, mnemonic,
2139 multiclass LogicalReg<bits<2> opc, bit N, string mnemonic,
2146 def Wrs : BaseLogicalSReg<opc, N, GPR32, logical_shifted_reg32, mnemonic,
2151 def Xrs : BaseLogicalSReg<opc, N, GPR64, logical_shifted_reg64, mnemonic,
2164 multiclass LogicalRegS<bits<2> opc, bit N, string mnemonic,
2170 def Wrs : BaseLogicalSReg<opc, N, GPR32, logical_shifted_reg32, mnemonic,
2174 def Xrs : BaseLogicalSReg<opc, N, GPR64, logical_shifted_reg64, mnemonic,
2391 class BaseLoadStoreUI<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2403 let Inst{23-22} = opc;
2411 multiclass LoadUI<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2414 def ui : BaseLoadStoreUI<sz, V, opc, (outs regtype:$Rt),
2423 multiclass StoreUI<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2426 def ui : BaseLoadStoreUI<sz, V, opc, (outs),
2445 class PrefetchUI<bits<2> sz, bit V, bits<2> opc, string asm, list<dag> pat>
2446 : BaseLoadStoreUI<sz, V, opc,
2465 class LoadLiteral<bits<2> opc, bit V, RegisterClass regtype, string asm>
2471 let Inst{31-30} = opc;
2480 class PrefetchLiteral<bits<2> opc, bit V, string asm, list<dag> pat>
2486 let Inst{31-30} = opc;
2576 class LoadStore8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2587 let Inst{23-22} = opc;
2602 multiclass Load8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2605 def roW : LoadStore8RO<sz, V, opc, regtype, asm,
2616 def roX : LoadStore8RO<sz, V, opc, regtype, asm,
2629 multiclass Store8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2632 def roW : LoadStore8RO<sz, V, opc, regtype, asm, (outs),
2642 def roX : LoadStore8RO<sz, V, opc, regtype, asm, (outs),
2654 class LoadStore16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2665 let Inst{23-22} = opc;
2676 multiclass Load16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2679 def roW : LoadStore16RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2689 def roX : LoadStore16RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2701 multiclass Store16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2704 def roW : LoadStore16RO<sz, V, opc, regtype, asm, (outs),
2714 def roX : LoadStore16RO<sz, V, opc, regtype, asm, (outs),
2726 class LoadStore32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2737 let Inst{23-22} = opc;
2748 multiclass Load32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2751 def roW : LoadStore32RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2761 def roX : LoadStore32RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2773 multiclass Store32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2776 def roW : LoadStore32RO<sz, V, opc, regtype, asm, (outs),
2786 def roX : LoadStore32RO<sz, V, opc, regtype, asm, (outs),
2798 class LoadStore64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2809 let Inst{23-22} = opc;
2820 multiclass Load64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2823 def roW : LoadStore64RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2833 def roX : LoadStore64RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2845 multiclass Store64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2848 def roW : LoadStore64RO<sz, V, opc, regtype, asm, (outs),
2858 def roX : LoadStore64RO<sz, V, opc, regtype, asm, (outs),
2870 class LoadStore128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2881 let Inst{23-22} = opc;
2892 multiclass Load128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2895 def roW : LoadStore128RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2905 def roX : LoadStore128RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2917 multiclass Store128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2920 def roW : LoadStore128RO<sz, V, opc, regtype, asm, (outs),
2930 def roX : LoadStore128RO<sz, V, opc, regtype, asm, (outs),
2943 class BasePrefetchRO<bits<2> sz, bit V, bits<2> opc, dag outs, dag ins,
2955 let Inst{23-22} = opc;
2966 multiclass PrefetchRO<bits<2> sz, bit V, bits<2> opc, string asm> {
2967 def roW : BasePrefetchRO<sz, V, opc, (outs),
2975 def roX : BasePrefetchRO<sz, V, opc, (outs),
2998 class BaseLoadStoreUnscale<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
3008 let Inst{23-22} = opc;
3018 multiclass LoadUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
3021 def i : BaseLoadStoreUnscale<sz, V, opc, (outs regtype:$Rt),
3029 multiclass StoreUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
3032 def i : BaseLoadStoreUnscale<sz, V, opc, (outs),
3041 multiclass PrefetchUnscaled<bits<2> sz, bit V, bits<2> opc, string asm,
3044 def i : BaseLoadStoreUnscale<sz, V, opc, (outs),
3057 class BaseLoadStoreUnprivileged<bits<2> sz, bit V, bits<2> opc,
3067 let Inst{23-22} = opc;
3077 multiclass LoadUnprivileged<bits<2> sz, bit V, bits<2> opc,
3080 def i : BaseLoadStoreUnprivileged<sz, V, opc, (outs regtype:$Rt),
3088 multiclass StoreUnprivileged<bits<2> sz, bit V, bits<2> opc,
3091 def i : BaseLoadStoreUnprivileged<sz, V, opc, (outs),
3104 class BaseLoadStorePreIdx<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
3114 let Inst{23-22} = opc;
3126 class LoadPreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
3128 : BaseLoadStorePreIdx<sz, V, opc,
3135 class StorePreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
3137 : BaseLoadStorePreIdx<sz, V, opc,
3150 class BaseLoadStorePostIdx<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
3160 let Inst{23-22} = opc;
3172 class LoadPostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
3174 : BaseLoadStorePostIdx<sz, V, opc,
3181 class StorePostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
3183 : BaseLoadStorePostIdx<sz, V, opc,
3199 class BaseLoadStorePairOffset<bits<2> opc, bit V, bit L, dag oops, dag iops,
3206 let Inst{31-30} = opc;
3219 multiclass LoadPairOffset<bits<2> opc, bit V, RegisterClass regtype,
3222 def i : BaseLoadStorePairOffset<opc, V, 1,
3233 multiclass StorePairOffset<bits<2> opc, bit V, RegisterClass regtype,
3236 def i : BaseLoadStorePairOffset<opc, V, 0, (outs),
3248 class BaseLoadStorePairPreIdx<bits<2> opc, bit V, bit L, dag oops, dag iops,
3255 let Inst{31-30} = opc;
3270 class LoadPairPreIdx<bits<2> opc, bit V, RegisterClass regtype,
3272 : BaseLoadStorePairPreIdx<opc, V, 1,
3278 class StorePairPreIdx<bits<2> opc, bit V, RegisterClass regtype,
3280 : BaseLoadStorePairPreIdx<opc, V, 0, (outs GPR64sp:$wback),
3289 class BaseLoadStorePairPostIdx<bits<2> opc, bit V, bit L, dag oops, dag iops,
3296 let Inst{31-30} = opc;
3311 class LoadPairPostIdx<bits<2> opc, bit V, RegisterClass regtype,
3313 : BaseLoadStorePairPostIdx<opc, V, 1,
3319 class StorePairPostIdx<bits<2> opc, bit V, RegisterClass regtype,
3321 : BaseLoadStorePairPostIdx<opc, V, 0, (outs GPR64sp:$wback),
3330 class BaseLoadStorePairNoAlloc<bits<2> opc, bit V, bit L, dag oops, dag iops,
3337 let Inst{31-30} = opc;
3350 multiclass LoadPairNoAlloc<bits<2> opc, bit V, RegisterClass regtype,
3353 def i : BaseLoadStorePairNoAlloc<opc, V, 1,
3364 multiclass StorePairNoAlloc<bits<2> opc, bit V, RegisterClass regtype,
3367 def i : BaseLoadStorePairNoAlloc<opc, V, 0, (outs),
4361 multiclass SIMDThreeSameVector<bit U, bits<5> opc, string asm,
4363 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b001, opc, V64,
4366 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b001, opc, V128,
4369 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b011, opc, V64,
4372 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b011, opc, V128,
4375 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b101, opc, V64,
4378 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b101, opc, V128,
4381 def v2i64 : BaseSIMDThreeSameVector<1, U, 0b111, opc, V128,
4387 multiclass SIMDThreeSameVectorBHS<bit U, bits<5> opc, string asm,
4389 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b001, opc, V64,
4392 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b001, opc, V128,
4395 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b011, opc, V64,
4398 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b011, opc, V128,
4401 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b101, opc, V64,
4404 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b101, opc, V128,
4409 multiclass SIMDThreeSameVectorBHSTied<bit U, bits<5> opc, string asm,
4411 def v8i8 : BaseSIMDThreeSameVectorTied<0, U, 0b001, opc, V64,
4415 def v16i8 : BaseSIMDThreeSameVectorTied<1, U, 0b001, opc, V128,
4419 def v4i16 : BaseSIMDThreeSameVectorTied<0, U, 0b011, opc, V64,
4423 def v8i16 : BaseSIMDThreeSameVectorTied<1, U, 0b011, opc, V128,
4427 def v2i32 : BaseSIMDThreeSameVectorTied<0, U, 0b101, opc, V64,
4431 def v4i32 : BaseSIMDThreeSameVectorTied<1, U, 0b101, opc, V128,
4438 multiclass SIMDThreeSameVectorB<bit U, bits<5> opc, string asm,
4440 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b001, opc, V64,
4443 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b001, opc, V128,
4450 multiclass SIMDThreeSameVectorFP<bit U, bit S, bits<3> opc,
4453 def v4f16 : BaseSIMDThreeSameVector<0, U, {S,0b10}, {0b00,opc}, V64,
4456 def v8f16 : BaseSIMDThreeSameVector<1, U, {S,0b10}, {0b00,opc}, V128,
4460 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0b01}, {0b11,opc}, V64,
4463 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0b01}, {0b11,opc}, V128,
4466 def v2f64 : BaseSIMDThreeSameVector<1, U, {S,0b11}, {0b11,opc}, V128,
4471 multiclass SIMDThreeSameVectorFPCmp<bit U, bit S, bits<3> opc,
4475 def v4f16 : BaseSIMDThreeSameVector<0, U, {S,0b10}, {0b00,opc}, V64,
4478 def v8f16 : BaseSIMDThreeSameVector<1, U, {S,0b10}, {0b00,opc}, V128,
4482 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0b01}, {0b11,opc}, V64,
4485 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0b01}, {0b11,opc}, V128,
4488 def v2f64 : BaseSIMDThreeSameVector<1, U, {S,0b11}, {0b11,opc}, V128,
4493 multiclass SIMDThreeSameVectorFPTied<bit U, bit S, bits<3> opc,
4496 def v4f16 : BaseSIMDThreeSameVectorTied<0, U, {S,0b10}, {0b00,opc}, V64,
4500 def v8f16 : BaseSIMDThreeSameVectorTied<1, U, {S,0b10}, {0b00,opc}, V128,
4505 def v2f32 : BaseSIMDThreeSameVectorTied<0, U, {S,0b01}, {0b11,opc}, V64,
4509 def v4f32 : BaseSIMDThreeSameVectorTied<1, U, {S,0b01}, {0b11,opc}, V128,
4513 def v2f64 : BaseSIMDThreeSameVectorTied<1, U, {S,0b11}, {0b11,opc}, V128,
4520 multiclass SIMDThreeSameVectorHS<bit U, bits<5> opc, string asm,
4522 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b011, opc, V64,
4525 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b011, opc, V128,
4528 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b101, opc, V64,
4531 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b101, opc, V128,
4655 multiclass SIMDTwoVectorBHS<bit U, bits<5> opc, string asm,
4657 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, 0b00, V64,
4660 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, 0b00, V128,
4663 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, 0b00, V64,
4666 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128,
4669 def v2i32 : BaseSIMDTwoSameVector<0, U, 0b10, opc, 0b00, V64,
4672 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, 0b00, V128,
4713 multiclass SIMDLongTwoVector<bit U, bits<5> opc, string asm,
4715 def v8i8_v4i16 : BaseSIMDTwoSameVector<0, U, 0b00, opc, 0b00, V64,
4718 def v16i8_v8i16 : BaseSIMDTwoSameVector<1, U, 0b00, opc, 0b00, V128,
4721 def v4i16_v2i32 : BaseSIMDTwoSameVector<0, U, 0b01, opc, 0b00, V64,
4724 def v8i16_v4i32 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128,
4727 def v2i32_v1i64 : BaseSIMDTwoSameVector<0, U, 0b10, opc, 0b00, V64,
4730 def v4i32_v2i64 : BaseSIMDTwoSameVector<1, U, 0b10, opc, 0b00, V128,
4735 multiclass SIMDLongTwoVectorTied<bit U, bits<5> opc, string asm,
4737 def v8i8_v4i16 : BaseSIMDTwoSameVectorTied<0, U, 0b00, opc, 0b00, V64,
4741 def v16i8_v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, 0b00, V128,
4745 def v4i16_v2i32 : BaseSIMDTwoSameVectorTied<0, U, 0b01, opc, 0b00, V64,
4749 def v8i16_v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, 0b00, V128,
4753 def v2i32_v1i64 : BaseSIMDTwoSameVectorTied<0, U, 0b10, opc, 0b00, V64,
4757 def v4i32_v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, 0b00, V128,
4764 multiclass SIMDTwoVectorBHSDTied<bit U, bits<5> opc, string asm,
4766 def v8i8 : BaseSIMDTwoSameVectorTied<0, U, 0b00, opc, 0b00, V64,
4769 def v16i8 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, 0b00, V128,
4772 def v4i16 : BaseSIMDTwoSameVectorTied<0, U, 0b01, opc, 0b00, V64,
4775 def v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, 0b00, V128,
4778 def v2i32 : BaseSIMDTwoSameVectorTied<0, U, 0b10, opc, 0b00, V64,
4781 def v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, 0b00, V128,
4784 def v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b11, opc, 0b00, V128,
4789 multiclass SIMDTwoVectorBHSD<bit U, bits<5> opc, string asm,
4791 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, 0b00, V64,
4794 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, 0b00, V128,
4797 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, 0b00, V64,
4800 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128,
4803 def v2i32 : BaseSIMDTwoSameVector<0, U, 0b10, opc, 0b00, V64,
4806 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, 0b00, V128,
4809 def v2i64 : BaseSIMDTwoSameVector<1, U, 0b11, opc, 0b00, V128,
4816 multiclass SIMDTwoVectorB<bit U, bits<2> size, bits<5> opc, string asm,
4818 def v8i8 : BaseSIMDTwoSameVector<0, U, size, opc, 0b00, V64,
4821 def v16i8 : BaseSIMDTwoSameVector<1, U, size, opc, 0b00, V128,
4828 multiclass SIMDTwoVectorBH<bit U, bits<5> opc, string asm,
4830 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, 0b00, V64,
4833 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, 0b00, V128,
4836 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, 0b00, V64,
4839 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128,
4846 multiclass SIMDTwoVectorFP<bit U, bit S, bits<5> opc, string asm,
4849 def v4f16 : BaseSIMDTwoSameVector<0, U, {S,1}, opc, 0b11, V64,
4852 def v8f16 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b11, V128,
4856 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, 0b00, V64,
4859 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, 0b00, V128,
4862 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b00, V128,
4868 multiclass SIMDTwoVectorS<bit U, bit S, bits<5> opc, string asm,
4870 def v2i32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, 0b00, V64,
4873 def v4i32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, 0b00, V128,
4879 multiclass SIMDTwoVectorFPToInt<bit U, bit S, bits<5> opc, string asm,
4882 def v4f16 : BaseSIMDTwoSameVector<0, U, {S,1}, opc, 0b11, V64,
4885 def v8f16 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b11, V128,
4889 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, 0b00, V64,
4892 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, 0b00, V128,
4895 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b00, V128,
4900 multiclass SIMDTwoVectorIntToFP<bit U, bit S, bits<5> opc, string asm,
4903 def v4f16 : BaseSIMDTwoSameVector<0, U, {S,1}, opc, 0b11, V64,
4906 def v8f16 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b11, V128,
4910 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, 0b00, V64,
4913 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, 0b00, V128,
4916 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b00, V128,
4966 multiclass SIMDMixedTwoVector<bit U, bits<5> opc, string asm,
4968 def v8i8 : BaseSIMDMixedTwoVector<0, U, 0b00, opc, V128, V64,
4971 def v16i8 : BaseSIMDMixedTwoVectorTied<1, U, 0b00, opc, V128, V128,
4973 def v4i16 : BaseSIMDMixedTwoVector<0, U, 0b01, opc, V128, V64,
4976 def v8i16 : BaseSIMDMixedTwoVectorTied<1, U, 0b01, opc, V128, V128,
4978 def v2i32 : BaseSIMDMixedTwoVector<0, U, 0b10, opc, V128, V64,
4981 def v4i32 : BaseSIMDMixedTwoVectorTied<1, U, 0b10, opc, V128, V128,
5021 multiclass SIMDCmpTwoVector<bit U, bits<5> opc, string asm,
5023 def v8i8rz : BaseSIMDCmpTwoVector<0, U, 0b00, 0b00, opc, V64,
5026 def v16i8rz : BaseSIMDCmpTwoVector<1, U, 0b00, 0b00, opc, V128,
5029 def v4i16rz : BaseSIMDCmpTwoVector<0, U, 0b01, 0b00, opc, V64,
5032 def v8i16rz : BaseSIMDCmpTwoVector<1, U, 0b01, 0b00, opc, V128,
5035 def v2i32rz : BaseSIMDCmpTwoVector<0, U, 0b10, 0b00, opc, V64,
5038 def v4i32rz : BaseSIMDCmpTwoVector<1, U, 0b10, 0b00, opc, V128,
5041 def v2i64rz : BaseSIMDCmpTwoVector<1, U, 0b11, 0b00, opc, V128,
5047 multiclass SIMDFPCmpTwoVector<bit U, bit S, bits<5> opc,
5051 def v4i16rz : BaseSIMDCmpTwoVector<0, U, {S,1}, 0b11, opc, V64,
5054 def v8i16rz : BaseSIMDCmpTwoVector<1, U, {S,1}, 0b11, opc, V128,
5058 def v2i32rz : BaseSIMDCmpTwoVector<0, U, {S,0}, 0b00, opc, V64,
5061 def v4i32rz : BaseSIMDCmpTwoVector<1, U, {S,0}, 0b00, opc, V128,
5064 def v2i64rz : BaseSIMDCmpTwoVector<1, U, {S,1}, 0b00, opc, V128,
5137 multiclass SIMDFPWidenTwoVector<bit U, bit S, bits<5> opc, string asm> {
5138 def v4i16 : BaseSIMDFPCvtTwoVector<0, U, {S,0}, opc, V128, V64,
5140 def v8i16 : BaseSIMDFPCvtTwoVector<1, U, {S,0}, opc, V128, V128,
5142 def v2i32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V128, V64,
5144 def v4i32 : BaseSIMDFPCvtTwoVector<1, U, {S,1}, opc, V128, V128,
5148 multiclass SIMDFPNarrowTwoVector<bit U, bit S, bits<5> opc, string asm> {
5149 def v4i16 : BaseSIMDFPCvtTwoVector<0, U, {S,0}, opc, V64, V128,
5151 def v8i16 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,0}, opc, V128, V128,
5153 def v2i32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V64, V128,
5155 def v4i32 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,1}, opc, V128, V128,
5159 multiclass SIMDFPInexactCvtTwoVector<bit U, bit S, bits<5> opc, string asm,
5161 def v2f32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V64, V128,
5164 def v4f32 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,1}, opc, V128, V128,
5232 multiclass SIMDNarrowThreeVectorBHS<bit U, bits<4> opc, string asm,
5234 def v8i16_v8i8 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
5238 def v8i16_v16i8 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
5242 def v4i32_v4i16 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
5246 def v4i32_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
5250 def v2i64_v2i32 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
5254 def v2i64_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
5279 multiclass SIMDDifferentThreeVectorBD<bit U, bits<4> opc, string asm,
5281 def v8i8 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
5285 def v16i8 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
5289 def v1i64 : BaseSIMDDifferentThreeVector<U, 0b110, opc,
5292 def v2i64 : BaseSIMDDifferentThreeVector<U, 0b111, opc,
5302 multiclass SIMDLongThreeVectorHS<bit U, bits<4> opc, string asm,
5304 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
5308 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
5313 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
5317 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
5324 multiclass SIMDLongThreeVectorBHSabdl<bit U, bits<4> opc, string asm,
5326 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
5331 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
5337 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
5342 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
5348 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
5353 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
5361 multiclass SIMDLongThreeVectorTiedBHSabal<bit U, bits<4> opc,
5364 def v8i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b000, opc,
5370 def v16i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
5377 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
5383 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
5390 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
5396 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
5405 multiclass SIMDLongThreeVectorBHS<bit U, bits<4> opc, string asm,
5407 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
5411 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
5416 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
5420 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
5425 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
5429 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
5436 multiclass SIMDLongThreeVectorTiedBHS<bit U, bits<4> opc,
5439 def v8i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b000, opc,
5444 def v16i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
5451 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
5456 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
5463 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
5468 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
5477 multiclass SIMDLongThreeVectorSQDMLXTiedHS<bit U, bits<4> opc, string asm,
5479 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
5486 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
5493 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
5500 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
5509 multiclass SIMDWideThreeVectorBHS<bit U, bits<4> opc, string asm,
5511 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
5515 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
5520 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
5524 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
5529 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
5533 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
5579 class BaseSIMDZipVector<bits<3> size, bits<3> opc, RegisterOperand regtype,
5596 let Inst{14-12} = opc;
5602 multiclass SIMDZipVector<bits<3>opc, string asm,
5604 def v8i8 : BaseSIMDZipVector<0b000, opc, V64,
5606 def v16i8 : BaseSIMDZipVector<0b001, opc, V128,
5608 def v4i16 : BaseSIMDZipVector<0b010, opc, V64,
5610 def v8i16 : BaseSIMDZipVector<0b011, opc, V128,
5612 def v2i32 : BaseSIMDZipVector<0b100, opc, V64,
5614 def v4i32 : BaseSIMDZipVector<0b101, opc, V128,
5616 def v2i64 : BaseSIMDZipVector<0b111, opc, V128,
5677 multiclass SIMDThreeScalarD<bit U, bits<5> opc, string asm,
5679 def v1i64 : BaseSIMDThreeScalar<U, 0b111, opc, FPR64, asm,
5683 multiclass SIMDThreeScalarBHSD<bit U, bits<5> opc, string asm,
5685 def v1i64 : BaseSIMDThreeScalar<U, 0b111, opc, FPR64, asm,
5687 def v1i32 : BaseSIMDThreeScalar<U, 0b101, opc, FPR32, asm, []>;
5688 def v1i16 : BaseSIMDThreeScalar<U, 0b011, opc, FPR16, asm, []>;
5689 def v1i8 : BaseSIMDThreeScalar<U, 0b001, opc, FPR8 , asm, []>;
5697 multiclass SIMDThreeScalarHS<bit U, bits<5> opc, string asm,
5699 def v1i32 : BaseSIMDThreeScalar<U, 0b101, opc, FPR32, asm,
5701 def v1i16 : BaseSIMDThreeScalar<U, 0b011, opc, FPR16, asm, []>;
5704 multiclass SIMDThreeScalarHSTied<bit U, bit R, bits<5> opc, string asm,
5706 def v1i32: BaseSIMDThreeScalarTied<U, 0b10, R, opc, (outs FPR32:$dst),
5709 def v1i16: BaseSIMDThreeScalarTied<U, 0b01, R, opc, (outs FPR16:$dst),
5714 multiclass SIMDFPThreeScalar<bit U, bit S, bits<3> opc, string asm,
5717 def #NAME#64 : BaseSIMDThreeScalar<U, {S,0b11}, {0b11,opc}, FPR64, asm,
5719 def #NAME#32 : BaseSIMDThreeScalar<U, {S,0b01}, {0b11,opc}, FPR32, asm,
5722 def #NAME#16 : BaseSIMDThreeScalar<U, {S,0b10}, {0b00,opc}, FPR16, asm,
5731 multiclass SIMDThreeScalarFPCmp<bit U, bit S, bits<3> opc, string asm,
5734 def #NAME#64 : BaseSIMDThreeScalar<U, {S,0b11}, {0b11,opc}, FPR64, asm,
5736 def #NAME#32 : BaseSIMDThreeScalar<U, {S,0b01}, {0b11,opc}, FPR32, asm,
5739 def #NAME#16 : BaseSIMDThreeScalar<U, {S,0b10}, {0b00,opc}, FPR16, asm,
5769 multiclass SIMDThreeScalarMixedHS<bit U, bits<5> opc, string asm,
5771 def i16 : BaseSIMDThreeScalarMixed<U, 0b01, opc,
5774 def i32 : BaseSIMDThreeScalarMixed<U, 0b10, opc,
5781 multiclass SIMDThreeScalarMixedTiedHS<bit U, bits<5> opc, string asm,
5783 def i16 : BaseSIMDThreeScalarMixed<U, 0b01, opc,
5787 def i32 : BaseSIMDThreeScalarMixed<U, 0b10, opc,
5876 multiclass SIMDCmpTwoScalarD<bit U, bits<5> opc, string asm,
5878 def v1i64rz : BaseSIMDCmpTwoScalar<U, 0b11, 0b00, opc, FPR64, asm, "0">;
5884 multiclass SIMDFPCmpTwoScalar<bit U, bit S, bits<5> opc, string asm,
5886 def v1i64rz : BaseSIMDCmpTwoScalar<U, {S,1}, 0b00, opc, FPR64, asm, "0.0">;
5887 def v1i32rz : BaseSIMDCmpTwoScalar<U, {S,0}, 0b00, opc, FPR32, asm, "0.0">;
5889 def v1i16rz : BaseSIMDCmpTwoScalar<U, {S,1}, 0b11, opc, FPR16, asm, "0.0">;
5905 multiclass SIMDTwoScalarD<bit U, bits<5> opc, string asm,
5907 def v1i64 : BaseSIMDTwoScalar<U, 0b11, 0b00, opc, FPR64, FPR64, asm,
5914 multiclass SIMDFPTwoScalar<bit U, bit S, bits<5> opc, string asm> {
5915 def v1i64 : BaseSIMDTwoScalar<U, {S,1}, 0b00, opc, FPR64, FPR64, asm,[]>;
5916 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, 0b00, opc, FPR32, FPR32, asm,[]>;
5918 def v1f16 : BaseSIMDTwoScalar<U, {S,1}, 0b11, opc, FPR16, FPR16, asm,[]>;
5922 multiclass SIMDFPTwoScalarCVT<bit U, bit S, bits<5> opc, string asm,
5924 def v1i64 : BaseSIMDTwoScalar<U, {S,1}, 0b00, opc, FPR64, FPR64, asm,
5926 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, 0b00, opc, FPR32, FPR32, asm,
5929 def v1i16 : BaseSIMDTwoScalar<U, {S,1}, 0b11, opc, FPR16, FPR16, asm,
5934 multiclass SIMDTwoScalarBHSD<bit U, bits<5> opc, string asm,
5937 def v1i64 : BaseSIMDTwoScalar<U, 0b11, 0b00, opc, FPR64, FPR64, asm,
5939 def v1i32 : BaseSIMDTwoScalar<U, 0b10, 0b00, opc, FPR32, FPR32, asm,
5941 def v1i16 : BaseSIMDTwoScalar<U, 0b01, 0b00, opc, FPR16, FPR16, asm, []>;
5942 def v1i8 : BaseSIMDTwoScalar<U, 0b00, 0b00, opc, FPR8 , FPR8 , asm, []>;
5949 multiclass SIMDTwoScalarBHSDTied<bit U, bits<5> opc, string asm,
5952 def v1i64 : BaseSIMDTwoScalarTied<U, 0b11, opc, FPR64, FPR64, asm,
5954 def v1i32 : BaseSIMDTwoScalarTied<U, 0b10, opc, FPR32, FPR32, asm,
5956 def v1i16 : BaseSIMDTwoScalarTied<U, 0b01, opc, FPR16, FPR16, asm, []>;
5957 def v1i8 : BaseSIMDTwoScalarTied<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
5967 multiclass SIMDTwoScalarMixedBHS<bit U, bits<5> opc, string asm,
5969 def v1i32 : BaseSIMDTwoScalar<U, 0b10, 0b00, opc, FPR32, FPR64, asm,
5971 def v1i16 : BaseSIMDTwoScalar<U, 0b01, 0b00, opc, FPR16, FPR32, asm, []>;
5972 def v1i8 : BaseSIMDTwoScalar<U, 0b00, 0b00, opc, FPR8 , FPR16, asm, []>;
5999 multiclass SIMDPairwiseScalarD<bit U, bits<5> opc, string asm> {
6000 def v2i64p : BaseSIMDPairwiseScalar<U, 0b11, opc, FPR64Op, V128,
6004 multiclass SIMDFPPairwiseScalar<bit S, bits<5> opc, string asm> {
6006 def v2i16p : BaseSIMDPairwiseScalar<0, {S,0}, opc, FPR16Op, V64,
6009 def v2i32p : BaseSIMDPairwiseScalar<1, {S,0}, opc, FPR32Op, V64,
6011 def v2i64p : BaseSIMDPairwiseScalar<1, {S,1}, opc, FPR64Op, V128,
6728 class BaseSIMDIndexed<bit Q, bit U, bit Scalar, bits<2> size, bits<4> opc,
6750 let Inst{15-12} = opc;
6758 class BaseSIMDIndexedTied<bit Q, bit U, bit Scalar, bits<2> size, bits<4> opc,
6780 let Inst{15-12} = opc;
6787 multiclass SIMDFPIndexed<bit U, bits<4> opc, string asm,
6790 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b00, opc,
6803 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b00, opc,
6817 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6829 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6841 def v2i64_indexed : BaseSIMDIndexed<1, U, 0, 0b11, opc,
6854 def v1i16_indexed : BaseSIMDIndexed<1, U, 1, 0b00, opc,
6868 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
6880 def v1i64_indexed : BaseSIMDIndexed<1, U, 1, 0b11, opc,
6945 multiclass SIMDFPIndexedTied<bit U, bits<4> opc, string asm> {
6947 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b00, opc, V64, V64,
6956 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b00, opc,
6967 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc, V64, V64,
6975 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6984 def v2i64_indexed : BaseSIMDIndexedTied<1, U, 0, 0b11, opc,
6994 def v1i16_indexed : BaseSIMDIndexedTied<1, U, 1, 0b00, opc,
7004 def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
7012 def v1i64_indexed : BaseSIMDIndexedTied<1, U, 1, 0b11, opc,
7021 multiclass SIMDIndexedHS<bit U, bits<4> opc, string asm,
7023 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc, V64, V64,
7035 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
7048 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
7060 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
7072 def v1i16_indexed : BaseSIMDIndexed<1, U, 1, 0b01, opc,
7081 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
7094 multiclass SIMDVectorIndexedHS<bit U, bits<4> opc, string asm,
7096 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
7109 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
7122 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
7134 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
7147 multiclass SIMDVectorIndexedHSTied<bit U, bits<4> opc, string asm,
7149 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc, V64, V64,
7161 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
7174 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
7186 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
7199 multiclass SIMDIndexedLongSD<bit U, bits<4> opc, string asm,
7201 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
7214 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
7229 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
7241 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
7254 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b01, opc,
7263 def v1i64_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
7272 multiclass SIMDIndexedLongSQDMLXSDTied<bit U, bits<4> opc, string asm,
7274 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
7304 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
7321 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
7336 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
7352 def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b01, opc,
7362 def v1i64_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
7378 multiclass SIMDVectorIndexedLongSD<bit U, bits<4> opc, string asm,
7381 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
7394 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
7409 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
7421 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
7436 multiclass SIMDVectorIndexedLongSDTied<bit U, bits<4> opc, string asm,
7439 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
7452 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
7467 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
7479 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
7500 class BaseSIMDScalarShift<bit U, bits<5> opc, bits<7> fixed_imm,
7513 let Inst{15-11} = opc;
7520 class BaseSIMDScalarShiftTied<bit U, bits<5> opc, bits<7> fixed_imm,
7533 let Inst{15-11} = opc;
7540 multiclass SIMDFPScalarRShift<bit U, bits<5> opc, string asm> {
7542 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
7547 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7552 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7558 multiclass SIMDScalarRShiftD<bit U, bits<5> opc, string asm,
7560 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7571 multiclass SIMDScalarRShiftDTied<bit U, bits<5> opc, string asm,
7573 def d : BaseSIMDScalarShiftTied<U, opc, {1,?,?,?,?,?,?},
7586 multiclass SIMDScalarLShiftD<bit U, bits<5> opc, string asm,
7588 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7597 multiclass SIMDScalarLShiftDTied<bit U, bits<5> opc, string asm> {
7598 def d : BaseSIMDScalarShiftTied<U, opc, {1,?,?,?,?,?,?},
7605 multiclass SIMDScalarRShiftBHS<bit U, bits<5> opc, string asm,
7607 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
7612 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
7617 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7624 multiclass SIMDScalarLShiftBHSD<bit U, bits<5> opc, string asm,
7626 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
7631 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
7636 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7642 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7652 multiclass SIMDScalarRShiftBHSD<bit U, bits<5> opc, string asm> {
7653 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
7658 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
7663 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7668 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7679 class BaseSIMDVectorShift<bit Q, bit U, bits<5> opc, bits<7> fixed_imm,
7695 let Inst{15-11} = opc;
7702 class BaseSIMDVectorShiftTied<bit Q, bit U, bits<5> opc, bits<7> fixed_imm,
7718 let Inst{15-11} = opc;
7724 multiclass SIMDVectorRShiftSD<bit U, bits<5> opc, string asm,
7727 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7735 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7743 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7751 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7759 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7768 multiclass SIMDVectorRShiftToFP<bit U, bits<5> opc, string asm,
7771 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7779 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7788 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7796 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7804 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7813 multiclass SIMDVectorRShiftNarrowBHS<bit U, bits<5> opc, string asm,
7815 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7823 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
7831 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7839 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
7847 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7855 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
7885 multiclass SIMDVectorLShiftBHSD<bit U, bits<5> opc, string asm,
7887 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7896 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
7905 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7914 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7923 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7932 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7941 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7951 multiclass SIMDVectorRShiftBHSD<bit U, bits<5> opc, string asm,
7953 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7962 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
7971 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7980 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7989 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7998 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
8007 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
8018 multiclass SIMDVectorRShiftBHSDTied<bit U, bits<5> opc, string asm,
8020 def v8i8_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,0,1,?,?,?},
8029 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
8038 def v4i16_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,1,?,?,?,?},
8047 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
8056 def v2i32_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,1,?,?,?,?,?},
8065 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
8074 def v2i64_shift : BaseSIMDVectorShiftTied<1, U, opc, {1,?,?,?,?,?,?},
8084 multiclass SIMDVectorLShiftBHSDTied<bit U, bits<5> opc, string asm,
8086 def v8i8_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,0,1,?,?,?},
8096 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
8106 def v4i16_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,1,?,?,?,?},
8116 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
8126 def v2i32_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,1,?,?,?,?,?},
8136 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
8146 def v2i64_shift : BaseSIMDVectorShiftTied<1, U, opc, {1,?,?,?,?,?,?},
8157 multiclass SIMDVectorLShiftLongBHSD<bit U, bits<5> opc, string asm,
8159 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
8166 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
8175 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
8182 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
8192 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
8199 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
9071 multiclass SIMDThreeSameVectorSQRDMLxHTiedHS<bit U, bits<5> opc, string asm,
9073 def v4i16 : BaseSIMDThreeSameVectorTiedR0<0, U, 0b01, opc, V64, asm, ".4h",
9078 def v8i16 : BaseSIMDThreeSameVectorTiedR0<1, U, 0b01, opc, V128, asm, ".8h",
9083 def v2i32 : BaseSIMDThreeSameVectorTiedR0<0, U, 0b10, opc, V64, asm, ".2s",
9088 def v4i32 : BaseSIMDThreeSameVectorTiedR0<1, U, 0b10, opc, V128, asm, ".4s",
9095 multiclass SIMDIndexedSQRDMLxHSDTied<bit U, bits<4> opc, string asm,
9097 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
9112 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
9127 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
9166 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
9200 def i16_indexed : BaseSIMDIndexedTied<1, U, 1, 0b01, opc,
9210 def i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
9232 class AESBase<bits<4> opc, string asm, dag outs, dag ins, string cstr,
9239 let Inst{15-12} = opc;
9245 class AESInst<bits<4> opc, string asm, Intrinsic OpNode>
9246 : AESBase<opc, asm, (outs V128:$Rd), (ins V128:$Rn), "",
9249 class AESTiedInst<bits<4> opc, string asm, Intrinsic OpNode>
9250 : AESBase<opc, asm, (outs V128:$dst), (ins V128:$Rd, V128:$Rn),
9256 class SHA3OpTiedInst<bits<3> opc, string asm, string dst_lhs_kind,
9268 let Inst{14-12} = opc;
9274 class SHATiedInstQSV<bits<3> opc, string asm, Intrinsic OpNode>
9275 : SHA3OpTiedInst<opc, asm, "", (outs FPR128:$dst),
9281 class SHATiedInstVVV<bits<3> opc, string asm, Intrinsic OpNode>
9282 : SHA3OpTiedInst<opc, asm, ".4s", (outs V128:$dst),
9288 class SHATiedInstQQV<bits<3> opc, string asm, Intrinsic OpNode>
9289 : SHA3OpTiedInst<opc, asm, "", (outs FPR128:$dst),
9296 class SHA2OpInst<bits<4> opc, string asm, string kind,
9305 let Inst{15-12} = opc;
9311 class SHATiedInstVV<bits<4> opc, string asm, Intrinsic OpNode>
9312 : SHA2OpInst<opc, asm, ".4s", "$Rd = $dst", (outs V128:$dst),
9317 class SHAInstSS<bits<4> opc, string asm, Intrinsic OpNode>
9318 : SHA2OpInst<opc, asm, "", "", (outs FPR32:$Rd), (ins FPR32:$Rn),
9413 bits<3> opc = 0b000;
9423 let Inst{14-12} = opc;
9445 bits<3> opc;
9455 let Inst{14-12} = opc;
9461 multiclass LDOPregister<bits<3> opc, string op, bits<1> Acq, bits<1> Rel,
9463 let Sz = 0b00, Acq = Acq, Rel = Rel, opc = opc in
9465 let Sz = 0b01, Acq = Acq, Rel = Rel, opc = opc in
9467 let Sz = 0b10, Acq = Acq, Rel = Rel, opc = opc in
9469 let Sz = 0b11, Acq = Acq, Rel = Rel, opc = opc in