41 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {  in getCalleeSavedRegs()
42   assert(MF && "Invalid MachineFunction pointer.");  in getCalleeSavedRegs()
43   if (MF->getFunction()->getCallingConv() == CallingConv::GHC)  in getCalleeSavedRegs()
47   if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg)  in getCalleeSavedRegs()
49   if (MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS)  in getCalleeSavedRegs()
50     return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR() ?  in getCalleeSavedRegs()
53   if (MF->getSubtarget<AArch64Subtarget>().getTargetLowering()  in getCalleeSavedRegs()
55       MF->getFunction()->getAttributes().hasAttrSomewhere(  in getCalleeSavedRegs()
58   if (MF->getFunction()->getCallingConv() == CallingConv::PreserveMost)  in getCalleeSavedRegs()
65     const MachineFunction *MF) const {  in getCalleeSavedRegsViaCopy()
66   assert(MF && "Invalid MachineFunction pointer.");  in getCalleeSavedRegsViaCopy()
67   if (MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&  in getCalleeSavedRegsViaCopy()
68       MF->getInfo<AArch64FunctionInfo>()->isSplitCSR())  in getCalleeSavedRegsViaCopy()
74 AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF,  in getCallPreservedMask()  argument
83   if (MF.getSubtarget<AArch64Subtarget>().getTargetLowering()  in getCallPreservedMask()
85       MF.getFunction()->getAttributes().hasAttrSomewhere(Attribute::SwiftError))  in getCallPreservedMask()
102 AArch64RegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,  in getThisReturnPreservedMask()  argument
116 AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {  in getReservedRegs()
117   const AArch64FrameLowering *TFI = getFrameLowering(MF);  in getReservedRegs()
126   if (TFI->hasFP(MF) || TT.isOSDarwin()) {  in getReservedRegs()
131   if (MF.getSubtarget<AArch64Subtarget>().isX18Reserved()) {  in getReservedRegs()
136   if (hasBasePointer(MF)) {  in getReservedRegs()
144 bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF,  in isReservedReg()  argument
146   const AArch64FrameLowering *TFI = getFrameLowering(MF);  in isReservedReg()
158     return MF.getSubtarget<AArch64Subtarget>().isX18Reserved();  in isReservedReg()
161     return TFI->hasFP(MF) || TT.isOSDarwin();  in isReservedReg()
164     return hasBasePointer(MF);  in isReservedReg()
171 AArch64RegisterInfo::getPointerRegClass(const MachineFunction &MF,  in getPointerRegClass()  argument
185 bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const {  in hasBasePointer()
186   const MachineFrameInfo *MFI = MF.getFrameInfo();  in hasBasePointer()
196     if (needsStackRealignment(MF))  in hasBasePointer()
212 AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const {  in getFrameRegister()
213   const AArch64FrameLowering *TFI = getFrameLowering(MF);  in getFrameRegister()
214   return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;  in getFrameRegister()
218     const MachineFunction &MF) const {  in requiresRegisterScavenging()
223     const MachineFunction &MF) const {  in requiresVirtualBaseRegisters()
228 AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {  in useFPForScavengingIndex()
229   const MachineFrameInfo *MFI = MF.getFrameInfo();  in useFPForScavengingIndex()
233   return MFI->hasVarSizedObjects() && !hasBasePointer(MF);  in useFPForScavengingIndex()
237     const MachineFunction &MF) const {  in requiresFrameIndexScavenging()
242 AArch64RegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {  in cannotEliminateFrame()
243   const MachineFrameInfo *MFI = MF.getFrameInfo();  in cannotEliminateFrame()
244   if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack())  in cannotEliminateFrame()
276   MachineFunction &MF = *MI->getParent()->getParent();  in needsFrameBaseReg()  local
277   const AArch64FrameLowering *TFI = getFrameLowering(MF);  in needsFrameBaseReg()
278   MachineFrameInfo *MFI = MF.getFrameInfo();  in needsFrameBaseReg()
298   if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset))  in needsFrameBaseReg()
332   const MachineFunction &MF = *MBB->getParent();  in materializeFrameBaseRegister()  local
334       MF.getSubtarget<AArch64Subtarget>().getInstrInfo();  in materializeFrameBaseRegister()
337   MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));  in materializeFrameBaseRegister()
355   const MachineFunction *MF = MI.getParent()->getParent();  in resolveFrameIndex()  local
357       MF->getSubtarget<AArch64Subtarget>().getInstrInfo();  in resolveFrameIndex()
370   MachineFunction &MF = *MBB.getParent();  in eliminateFrameIndex()  local
372       MF.getSubtarget<AArch64Subtarget>().getInstrInfo();  in eliminateFrameIndex()
373   const AArch64FrameLowering *TFI = getFrameLowering(MF);  in eliminateFrameIndex()
382     Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,  in eliminateFrameIndex()
391   Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg);  in eliminateFrameIndex()
402       MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);  in eliminateFrameIndex()
408                                                   MachineFunction &MF) const {  in getRegPressureLimit()
409   const AArch64FrameLowering *TFI = getFrameLowering(MF);  in getRegPressureLimit()
423               - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP  in getRegPressureLimit()
424               - MF.getSubtarget<AArch64Subtarget>()  in getRegPressureLimit()
426               - hasBasePointer(MF);  // X19  in getRegPressureLimit()