326 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const {  in getVgprClassId()
328   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);  in getVgprClassId()
329   switch (Width) {  in getVgprClassId()
337 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const {  in getSgprClassId()
339   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);  in getSgprClassId()
340   switch (Width) {  in getSgprClassId()
348 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const {  in getTtmpClassId()
350   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);  in getTtmpClassId()
351   switch (Width) {  in getTtmpClassId()
359 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const {  in decodeSrcOp()  argument
364     return createRegOperand(getVgprClassId(Width), Val - VGPR_MIN);  in decodeSrcOp()
368     return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);  in decodeSrcOp()
371     return createSRegOperand(getTtmpClassId(Width), Val - TTMP_MIN);  in decodeSrcOp()
374   assert(Width == OPW32 || Width == OPW64);  in decodeSrcOp()
375   const bool Is32 = (Width == OPW32);  in decodeSrcOp()