Lines Matching refs:SDValue

34   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
35   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
37                           SmallVectorImpl<SDValue> &Results,
39   SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
43                                SmallVectorImpl<SDValue> &InVals) const override;
57   SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT, const SDLoc &DL,
62   SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SelectionDAG &DAG,
64   SDValue vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const;
66   SDValue lowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
67   SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
68   SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
69   SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
71   SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
73   SDValue lowerPrivateTruncStore(StoreSDNode *Store, SelectionDAG &DAG) const;
74   SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
75   SDValue LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const;
77   SDValue lowerPrivateExtLoad(SDValue Op, SelectionDAG &DAG) const;
78   SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
79   SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
80   SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
81   SDValue LowerSHLParts(SDValue Op, SelectionDAG &DAG) const;
82   SDValue LowerSRXParts(SDValue Op, SelectionDAG &DAG) const;
83   SDValue LowerUADDSUBO(SDValue Op, SelectionDAG &DAG,
86   SDValue stackPtrToRegIndex(SDValue Ptr, unsigned StackWidth,
90   bool isZero(SDValue Op) const;
91   bool isHWTrueValue(SDValue Op) const;
92   bool isHWFalseValue(SDValue Op) const;
94  bool FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src,
95                   SDValue &Neg, SDValue &Abs, SDValue &Sel, SDValue &Imm,