70                    const MachineRegisterInfo &MRI) {  in isVGPR()  argument
75     return TRI.hasVGPRs(MRI.getRegClass(MO->getReg()));  in isVGPR()
82                       const MachineRegisterInfo &MRI) {  in canShrink()  argument
96         if (!isVGPR(Src2, TRI, MRI) ||  in canShrink()
110   if (Src1 && (!isVGPR(Src1, TRI, MRI) || (Src1Mod && Src1Mod->getImm() != 0)))  in canShrink()
130                            MachineRegisterInfo &MRI, bool TryToCommute = true) {  in foldImmediates()  argument
132   if (!MRI.isSSA())  in foldImmediates()
150   if (Src0.isReg() && !isVGPR(&Src0, TRI, MRI))  in foldImmediates()
154   if (Src0.isReg() && MRI.hasOneUse(Src0.getReg())) {  in foldImmediates()
156     MachineInstr *Def = MRI.getUniqueVRegDef(Reg);  in foldImmediates()
166         if (MRI.use_empty(Reg))  in foldImmediates()
176     foldImmediates(MI, TII, MRI, false);  in foldImmediates()
201   MachineRegisterInfo &MRI = MF.getRegInfo();  in runOnMachineFunction()  local
284           MRI.setRegAllocationHint(Dest.getReg(), 0, Src0.getReg());  in runOnMachineFunction()
312       if (!canShrink(MI, TII, TRI, MRI)) {  in runOnMachineFunction()
316             !canShrink(MI, TII, TRI, MRI))  in runOnMachineFunction()
338           MRI.setRegAllocationHint(MI.getOperand(0).getReg(), 0, AMDGPU::VCC);  in runOnMachineFunction()
354           MRI.setRegAllocationHint(SReg, 0, AMDGPU::VCC);  in runOnMachineFunction()
403       foldImmediates(*Inst32, TII, MRI);  in runOnMachineFunction()