Lines Matching refs:DebugLoc
71 const DebugLoc &DL, unsigned Reg, unsigned Lane,
76 const DebugLoc &DL, unsigned DReg,
81 const DebugLoc &DL, unsigned Ssub0, unsigned Ssub1);
85 const DebugLoc &DL, unsigned Reg1,
90 const DebugLoc &DL, unsigned DReg,
95 const DebugLoc &DL);
428 const DebugLoc &DL, unsigned Reg, in createDupLane()
446 const DebugLoc &DL, unsigned DReg, unsigned Lane, in createExtractSubreg()
461 const DebugLoc &DL, unsigned Reg1, unsigned Reg2) { in createRegSequence()
478 const DebugLoc &DL, unsigned Ssub0, in createVExt()
493 const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) { in createInsertSubreg()
509 const DebugLoc &DL) { in createImplicitDef()
524 DebugLoc DL = MI->getDebugLoc(); in optimizeAllLanesPattern()