Lines Matching refs:N0
4707 SDValue N0 = DAG.getNode(ISD::BITCAST, DL, VT8Bit, N->getOperand(0)); in getCTPOP16BitCounts() local
4708 SDValue N1 = DAG.getNode(ISD::CTPOP, DL, VT8Bit, N0); in getCTPOP16BitCounts()
4767 SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16); in lowerCTPOP32BitElements() local
4768 SDValue N1 = DAG.getNode(ISD::ADD, DL, VT16Bit, Counts16, N0); in lowerCTPOP32BitElements()
6616 SDNode *N0 = N->getOperand(0).getNode(); in isAddSubSExt() local
6618 return N0->hasOneUse() && N1->hasOneUse() && in isAddSubSExt()
6619 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); in isAddSubSExt()
6627 SDNode *N0 = N->getOperand(0).getNode(); in isAddSubZExt() local
6629 return N0->hasOneUse() && N1->hasOneUse() && in isAddSubZExt()
6630 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); in isAddSubZExt()
6641 SDNode *N0 = Op.getOperand(0).getNode(); in LowerMUL() local
6645 bool isN0SExt = isSignExtended(N0, DAG); in LowerMUL()
6650 bool isN0ZExt = isZeroExtended(N0, DAG); in LowerMUL()
6657 if (isN1SExt && isAddSubSExt(N0, DAG)) { in LowerMUL()
6660 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) { in LowerMUL()
6664 std::swap(N0, N1); in LowerMUL()
6685 Op0 = SkipExtensionForVMULL(N0, DAG); in LowerMUL()
6700 SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG); in LowerMUL()
6701 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG); in LowerMUL()
6703 return DAG.getNode(N0->getOpcode(), DL, VT, in LowerMUL()
6741 static SDValue LowerSDIV_v4i16(SDValue N0, SDValue N1, const SDLoc &dl, in LowerSDIV_v4i16() argument
6749 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
6751 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); in LowerSDIV_v4i16()
6768 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); in LowerSDIV_v4i16()
6769 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
6771 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); in LowerSDIV_v4i16()
6772 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); in LowerSDIV_v4i16()
6775 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
6776 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); in LowerSDIV_v4i16()
6777 return N0; in LowerSDIV_v4i16()
6786 SDValue N0 = Op.getOperand(0); in LowerSDIV() local
6791 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0); in LowerSDIV()
6794 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
6798 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
6803 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16 in LowerSDIV()
6806 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerSDIV()
6807 N0 = LowerCONCAT_VECTORS(N0, DAG); in LowerSDIV()
6809 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0); in LowerSDIV()
6810 return N0; in LowerSDIV()
6812 return LowerSDIV_v4i16(N0, N1, dl, DAG); in LowerSDIV()
6822 SDValue N0 = Op.getOperand(0); in LowerUDIV() local
6827 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0); in LowerUDIV()
6830 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerUDIV()
6834 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerUDIV()
6839 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16 in LowerUDIV()
6842 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerUDIV()
6843 N0 = LowerCONCAT_VECTORS(N0, DAG); in LowerUDIV()
6845 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8, in LowerUDIV()
6848 N0); in LowerUDIV()
6849 return N0; in LowerUDIV()
6855 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0); in LowerUDIV()
6857 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); in LowerUDIV()
6879 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); in LowerUDIV()
6880 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); in LowerUDIV()
6882 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); in LowerUDIV()
6883 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); in LowerUDIV()
6886 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerUDIV()
6887 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); in LowerUDIV()
6888 return N0; in LowerUDIV()
8706 SDValue N0 = N->getOperand(0); in combineSelectAndUseCommutative() local
8708 if (N0.getNode()->hasOneUse()) in combineSelectAndUseCommutative()
8709 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes)) in combineSelectAndUseCommutative()
8712 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes)) in combineSelectAndUseCommutative()
8719 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1, in AddCombineToVPADDL() argument
8726 || N0.getOpcode() != ISD::BUILD_VECTOR in AddCombineToVPADDL()
8742 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in AddCombineToVPADDL()
8744 SDValue Vec = N0->getOperand(0)->getOperand(0); in AddCombineToVPADDL()
8751 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) { in AddCombineToVPADDL()
8752 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT in AddCombineToVPADDL()
8755 SDValue ExtVec0 = N0->getOperand(i); in AddCombineToVPADDL()
9045 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, in PerformADDCombineWithOperands() argument
9050 if (SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget)) in PerformADDCombineWithOperands()
9054 if (N0.getNode()->hasOneUse()) in PerformADDCombineWithOperands()
9055 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI)) in PerformADDCombineWithOperands()
9065 SDValue N0 = N->getOperand(0); in PerformADDCombine() local
9069 if (SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget)) in PerformADDCombine()
9073 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget); in PerformADDCombine()
9080 SDValue N0 = N->getOperand(0); in PerformSUBCombine() local
9085 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI)) in PerformSUBCombine()
9113 SDValue N0 = N->getOperand(0); in PerformVMULCombine() local
9115 unsigned Opcode = N0.getOpcode(); in PerformVMULCombine()
9122 std::swap(N0, N1); in PerformVMULCombine()
9125 if (N0 == N1) in PerformVMULCombine()
9130 SDValue N00 = N0->getOperand(0); in PerformVMULCombine()
9131 SDValue N01 = N0->getOperand(1); in PerformVMULCombine()
9305 SDValue N0 = N->getOperand(0); in PerformORCombine() local
9306 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse()) in PerformORCombine()
9318 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1)); in PerformORCombine()
9334 N0->getOperand(1), in PerformORCombine()
9335 N0->getOperand(0), in PerformORCombine()
9364 SDValue N00 = N0.getOperand(0); in PerformORCombine()
9369 SDValue MaskOp = N0.getOperand(1); in PerformORCombine()
10705 SDValue N0 = N->getOperand(0); in PerformShiftCombine() local
10706 if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP && in PerformShiftCombine()
10707 DAG.MaskedValueIsZero(N0.getOperand(0), in PerformShiftCombine()
10709 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, N0, N1); in PerformShiftCombine()
10749 SDValue N0 = N->getOperand(0); in PerformExtendCombine() local
10755 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in PerformExtendCombine()
10756 SDValue Vec = N0.getOperand(0); in PerformExtendCombine()
10757 SDValue Lane = N0.getOperand(1); in PerformExtendCombine()
10759 EVT EltVT = N0.getValueType(); in PerformExtendCombine()