Lines Matching refs:ARM
422 case ARM::HVC: { in checkDecodedInstruction()
442 assert(!STI.getFeatureBits()[ARM::ModeThumb] && in getInstruction()
579 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { in AddThumb1SBit()
581 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
586 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
602 case ARM::tBcc: in AddThumbPredicate()
603 case ARM::t2Bcc: in AddThumbPredicate()
604 case ARM::tCBZ: in AddThumbPredicate()
605 case ARM::tCBNZ: in AddThumbPredicate()
606 case ARM::tCPS: in AddThumbPredicate()
607 case ARM::t2CPS3p: in AddThumbPredicate()
608 case ARM::t2CPS2p: in AddThumbPredicate()
609 case ARM::t2CPS1p: in AddThumbPredicate()
610 case ARM::tMOVSr: in AddThumbPredicate()
611 case ARM::tSETEND: in AddThumbPredicate()
619 case ARM::t2HINT: in AddThumbPredicate()
620 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) in AddThumbPredicate()
623 case ARM::tB: in AddThumbPredicate()
624 case ARM::t2B: in AddThumbPredicate()
625 case ARM::t2TBB: in AddThumbPredicate()
626 case ARM::t2TBH: in AddThumbPredicate()
656 MI.insert(I, MCOperand::createReg(ARM::CPSR)); in AddThumbPredicate()
666 MI.insert(I, MCOperand::createReg(ARM::CPSR)); in AddThumbPredicate()
692 I->setReg(ARM::CPSR); in UpdateThumbVFPPredicate()
705 assert(STI.getFeatureBits()[ARM::ModeThumb] && in getInstruction()
740 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) in getInstruction()
748 if (MI.getOpcode() == ARM::t2IT) { in getInstruction()
875 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
876 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
877 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
878 ARM::R12, ARM::SP, ARM::LR, ARM::PC
911 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); in DecodeGPRwithAPSRRegisterClass()
927 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
928 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
951 Register = ARM::R0; in DecodetcGPRRegisterClass()
954 Register = ARM::R1; in DecodetcGPRRegisterClass()
957 Register = ARM::R2; in DecodetcGPRRegisterClass()
960 Register = ARM::R3; in DecodetcGPRRegisterClass()
963 Register = ARM::R9; in DecodetcGPRRegisterClass()
966 Register = ARM::R12; in DecodetcGPRRegisterClass()
983 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) in DecoderGPRRegisterClass()
991 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
992 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
993 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
994 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
995 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
996 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
997 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
998 ARM::S28, ARM::S29, ARM::S30, ARM::S31
1012 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1013 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1014 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1015 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1016 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1017 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1018 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1019 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1027 bool hasD16 = featureBits[ARM::FeatureD16]; in DecodeDPRRegisterClass()
1053 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1054 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1055 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1056 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1072 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1073 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1074 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1075 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1076 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1077 ARM::Q15
1091 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1092 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1093 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1094 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1095 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1096 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1097 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1098 ARM::D28_D30, ARM::D29_D31
1117 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) in DecodePredicateOperand()
1123 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); in DecodePredicateOperand()
1130 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); in DecodeCCOutOperand()
1217 case ARM::LDMIA_UPD: in DecodeRegListOperand()
1218 case ARM::LDMDB_UPD: in DecodeRegListOperand()
1219 case ARM::LDMIB_UPD: in DecodeRegListOperand()
1220 case ARM::LDMDA_UPD: in DecodeRegListOperand()
1221 case ARM::t2LDMIA_UPD: in DecodeRegListOperand()
1222 case ARM::t2LDMDB_UPD: in DecodeRegListOperand()
1223 case ARM::t2STMIA_UPD: in DecodeRegListOperand()
1224 case ARM::t2STMDB_UPD: in DecodeRegListOperand()
1333 case ARM::LDC_OFFSET: in DecodeCopMemInstruction()
1334 case ARM::LDC_PRE: in DecodeCopMemInstruction()
1335 case ARM::LDC_POST: in DecodeCopMemInstruction()
1336 case ARM::LDC_OPTION: in DecodeCopMemInstruction()
1337 case ARM::LDCL_OFFSET: in DecodeCopMemInstruction()
1338 case ARM::LDCL_PRE: in DecodeCopMemInstruction()
1339 case ARM::LDCL_POST: in DecodeCopMemInstruction()
1340 case ARM::LDCL_OPTION: in DecodeCopMemInstruction()
1341 case ARM::STC_OFFSET: in DecodeCopMemInstruction()
1342 case ARM::STC_PRE: in DecodeCopMemInstruction()
1343 case ARM::STC_POST: in DecodeCopMemInstruction()
1344 case ARM::STC_OPTION: in DecodeCopMemInstruction()
1345 case ARM::STCL_OFFSET: in DecodeCopMemInstruction()
1346 case ARM::STCL_PRE: in DecodeCopMemInstruction()
1347 case ARM::STCL_POST: in DecodeCopMemInstruction()
1348 case ARM::STCL_OPTION: in DecodeCopMemInstruction()
1349 case ARM::t2LDC_OFFSET: in DecodeCopMemInstruction()
1350 case ARM::t2LDC_PRE: in DecodeCopMemInstruction()
1351 case ARM::t2LDC_POST: in DecodeCopMemInstruction()
1352 case ARM::t2LDC_OPTION: in DecodeCopMemInstruction()
1353 case ARM::t2LDCL_OFFSET: in DecodeCopMemInstruction()
1354 case ARM::t2LDCL_PRE: in DecodeCopMemInstruction()
1355 case ARM::t2LDCL_POST: in DecodeCopMemInstruction()
1356 case ARM::t2LDCL_OPTION: in DecodeCopMemInstruction()
1357 case ARM::t2STC_OFFSET: in DecodeCopMemInstruction()
1358 case ARM::t2STC_PRE: in DecodeCopMemInstruction()
1359 case ARM::t2STC_POST: in DecodeCopMemInstruction()
1360 case ARM::t2STC_OPTION: in DecodeCopMemInstruction()
1361 case ARM::t2STCL_OFFSET: in DecodeCopMemInstruction()
1362 case ARM::t2STCL_PRE: in DecodeCopMemInstruction()
1363 case ARM::t2STCL_POST: in DecodeCopMemInstruction()
1364 case ARM::t2STCL_OPTION: in DecodeCopMemInstruction()
1374 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) in DecodeCopMemInstruction()
1383 case ARM::t2LDC2_OFFSET: in DecodeCopMemInstruction()
1384 case ARM::t2LDC2L_OFFSET: in DecodeCopMemInstruction()
1385 case ARM::t2LDC2_PRE: in DecodeCopMemInstruction()
1386 case ARM::t2LDC2L_PRE: in DecodeCopMemInstruction()
1387 case ARM::t2STC2_OFFSET: in DecodeCopMemInstruction()
1388 case ARM::t2STC2L_OFFSET: in DecodeCopMemInstruction()
1389 case ARM::t2STC2_PRE: in DecodeCopMemInstruction()
1390 case ARM::t2STC2L_PRE: in DecodeCopMemInstruction()
1391 case ARM::LDC2_OFFSET: in DecodeCopMemInstruction()
1392 case ARM::LDC2L_OFFSET: in DecodeCopMemInstruction()
1393 case ARM::LDC2_PRE: in DecodeCopMemInstruction()
1394 case ARM::LDC2L_PRE: in DecodeCopMemInstruction()
1395 case ARM::STC2_OFFSET: in DecodeCopMemInstruction()
1396 case ARM::STC2L_OFFSET: in DecodeCopMemInstruction()
1397 case ARM::STC2_PRE: in DecodeCopMemInstruction()
1398 case ARM::STC2L_PRE: in DecodeCopMemInstruction()
1399 case ARM::t2LDC_OFFSET: in DecodeCopMemInstruction()
1400 case ARM::t2LDCL_OFFSET: in DecodeCopMemInstruction()
1401 case ARM::t2LDC_PRE: in DecodeCopMemInstruction()
1402 case ARM::t2LDCL_PRE: in DecodeCopMemInstruction()
1403 case ARM::t2STC_OFFSET: in DecodeCopMemInstruction()
1404 case ARM::t2STCL_OFFSET: in DecodeCopMemInstruction()
1405 case ARM::t2STC_PRE: in DecodeCopMemInstruction()
1406 case ARM::t2STCL_PRE: in DecodeCopMemInstruction()
1407 case ARM::LDC_OFFSET: in DecodeCopMemInstruction()
1408 case ARM::LDCL_OFFSET: in DecodeCopMemInstruction()
1409 case ARM::LDC_PRE: in DecodeCopMemInstruction()
1410 case ARM::LDCL_PRE: in DecodeCopMemInstruction()
1411 case ARM::STC_OFFSET: in DecodeCopMemInstruction()
1412 case ARM::STCL_OFFSET: in DecodeCopMemInstruction()
1413 case ARM::STC_PRE: in DecodeCopMemInstruction()
1414 case ARM::STCL_PRE: in DecodeCopMemInstruction()
1418 case ARM::t2LDC2_POST: in DecodeCopMemInstruction()
1419 case ARM::t2LDC2L_POST: in DecodeCopMemInstruction()
1420 case ARM::t2STC2_POST: in DecodeCopMemInstruction()
1421 case ARM::t2STC2L_POST: in DecodeCopMemInstruction()
1422 case ARM::LDC2_POST: in DecodeCopMemInstruction()
1423 case ARM::LDC2L_POST: in DecodeCopMemInstruction()
1424 case ARM::STC2_POST: in DecodeCopMemInstruction()
1425 case ARM::STC2L_POST: in DecodeCopMemInstruction()
1426 case ARM::t2LDC_POST: in DecodeCopMemInstruction()
1427 case ARM::t2LDCL_POST: in DecodeCopMemInstruction()
1428 case ARM::t2STC_POST: in DecodeCopMemInstruction()
1429 case ARM::t2STCL_POST: in DecodeCopMemInstruction()
1430 case ARM::LDC_POST: in DecodeCopMemInstruction()
1431 case ARM::LDCL_POST: in DecodeCopMemInstruction()
1432 case ARM::STC_POST: in DecodeCopMemInstruction()
1433 case ARM::STCL_POST: in DecodeCopMemInstruction()
1444 case ARM::LDC_OFFSET: in DecodeCopMemInstruction()
1445 case ARM::LDC_PRE: in DecodeCopMemInstruction()
1446 case ARM::LDC_POST: in DecodeCopMemInstruction()
1447 case ARM::LDC_OPTION: in DecodeCopMemInstruction()
1448 case ARM::LDCL_OFFSET: in DecodeCopMemInstruction()
1449 case ARM::LDCL_PRE: in DecodeCopMemInstruction()
1450 case ARM::LDCL_POST: in DecodeCopMemInstruction()
1451 case ARM::LDCL_OPTION: in DecodeCopMemInstruction()
1452 case ARM::STC_OFFSET: in DecodeCopMemInstruction()
1453 case ARM::STC_PRE: in DecodeCopMemInstruction()
1454 case ARM::STC_POST: in DecodeCopMemInstruction()
1455 case ARM::STC_OPTION: in DecodeCopMemInstruction()
1456 case ARM::STCL_OFFSET: in DecodeCopMemInstruction()
1457 case ARM::STCL_PRE: in DecodeCopMemInstruction()
1458 case ARM::STCL_POST: in DecodeCopMemInstruction()
1459 case ARM::STCL_OPTION: in DecodeCopMemInstruction()
1486 case ARM::STR_POST_IMM: in DecodeAddrMode2IdxInstruction()
1487 case ARM::STR_POST_REG: in DecodeAddrMode2IdxInstruction()
1488 case ARM::STRB_POST_IMM: in DecodeAddrMode2IdxInstruction()
1489 case ARM::STRB_POST_REG: in DecodeAddrMode2IdxInstruction()
1490 case ARM::STRT_POST_REG: in DecodeAddrMode2IdxInstruction()
1491 case ARM::STRT_POST_IMM: in DecodeAddrMode2IdxInstruction()
1492 case ARM::STRBT_POST_REG: in DecodeAddrMode2IdxInstruction()
1493 case ARM::STRBT_POST_IMM: in DecodeAddrMode2IdxInstruction()
1506 case ARM::LDR_POST_IMM: in DecodeAddrMode2IdxInstruction()
1507 case ARM::LDR_POST_REG: in DecodeAddrMode2IdxInstruction()
1508 case ARM::LDRB_POST_IMM: in DecodeAddrMode2IdxInstruction()
1509 case ARM::LDRB_POST_REG: in DecodeAddrMode2IdxInstruction()
1510 case ARM::LDRBT_POST_REG: in DecodeAddrMode2IdxInstruction()
1511 case ARM::LDRBT_POST_IMM: in DecodeAddrMode2IdxInstruction()
1512 case ARM::LDRT_POST_REG: in DecodeAddrMode2IdxInstruction()
1513 case ARM::LDRT_POST_IMM: in DecodeAddrMode2IdxInstruction()
1639 case ARM::STRD: in DecodeAddrMode3Instruction()
1640 case ARM::STRD_PRE: in DecodeAddrMode3Instruction()
1641 case ARM::STRD_POST: in DecodeAddrMode3Instruction()
1642 case ARM::LDRD: in DecodeAddrMode3Instruction()
1643 case ARM::LDRD_PRE: in DecodeAddrMode3Instruction()
1644 case ARM::LDRD_POST: in DecodeAddrMode3Instruction()
1651 case ARM::STRD: in DecodeAddrMode3Instruction()
1652 case ARM::STRD_PRE: in DecodeAddrMode3Instruction()
1653 case ARM::STRD_POST: in DecodeAddrMode3Instruction()
1666 case ARM::STRH: in DecodeAddrMode3Instruction()
1667 case ARM::STRH_PRE: in DecodeAddrMode3Instruction()
1668 case ARM::STRH_POST: in DecodeAddrMode3Instruction()
1676 case ARM::LDRD: in DecodeAddrMode3Instruction()
1677 case ARM::LDRD_PRE: in DecodeAddrMode3Instruction()
1678 case ARM::LDRD_POST: in DecodeAddrMode3Instruction()
1693 case ARM::LDRH: in DecodeAddrMode3Instruction()
1694 case ARM::LDRH_PRE: in DecodeAddrMode3Instruction()
1695 case ARM::LDRH_POST: in DecodeAddrMode3Instruction()
1708 case ARM::LDRSH: in DecodeAddrMode3Instruction()
1709 case ARM::LDRSH_PRE: in DecodeAddrMode3Instruction()
1710 case ARM::LDRSH_POST: in DecodeAddrMode3Instruction()
1711 case ARM::LDRSB: in DecodeAddrMode3Instruction()
1712 case ARM::LDRSB_PRE: in DecodeAddrMode3Instruction()
1713 case ARM::LDRSB_POST: in DecodeAddrMode3Instruction()
1738 case ARM::STRD: in DecodeAddrMode3Instruction()
1739 case ARM::STRD_PRE: in DecodeAddrMode3Instruction()
1740 case ARM::STRD_POST: in DecodeAddrMode3Instruction()
1741 case ARM::STRH: in DecodeAddrMode3Instruction()
1742 case ARM::STRH_PRE: in DecodeAddrMode3Instruction()
1743 case ARM::STRH_POST: in DecodeAddrMode3Instruction()
1755 case ARM::STRD: in DecodeAddrMode3Instruction()
1756 case ARM::STRD_PRE: in DecodeAddrMode3Instruction()
1757 case ARM::STRD_POST: in DecodeAddrMode3Instruction()
1758 case ARM::LDRD: in DecodeAddrMode3Instruction()
1759 case ARM::LDRD_PRE: in DecodeAddrMode3Instruction()
1760 case ARM::LDRD_POST: in DecodeAddrMode3Instruction()
1771 case ARM::LDRD: in DecodeAddrMode3Instruction()
1772 case ARM::LDRD_PRE: in DecodeAddrMode3Instruction()
1773 case ARM::LDRD_POST: in DecodeAddrMode3Instruction()
1774 case ARM::LDRH: in DecodeAddrMode3Instruction()
1775 case ARM::LDRH_PRE: in DecodeAddrMode3Instruction()
1776 case ARM::LDRH_POST: in DecodeAddrMode3Instruction()
1777 case ARM::LDRSH: in DecodeAddrMode3Instruction()
1778 case ARM::LDRSH_PRE: in DecodeAddrMode3Instruction()
1779 case ARM::LDRSH_POST: in DecodeAddrMode3Instruction()
1780 case ARM::LDRSB: in DecodeAddrMode3Instruction()
1781 case ARM::LDRSB_PRE: in DecodeAddrMode3Instruction()
1782 case ARM::LDRSB_POST: in DecodeAddrMode3Instruction()
1783 case ARM::LDRHTr: in DecodeAddrMode3Instruction()
1784 case ARM::LDRSBTr: in DecodeAddrMode3Instruction()
1875 case ARM::LDMDA: in DecodeMemMultipleWritebackInstruction()
1876 Inst.setOpcode(ARM::RFEDA); in DecodeMemMultipleWritebackInstruction()
1878 case ARM::LDMDA_UPD: in DecodeMemMultipleWritebackInstruction()
1879 Inst.setOpcode(ARM::RFEDA_UPD); in DecodeMemMultipleWritebackInstruction()
1881 case ARM::LDMDB: in DecodeMemMultipleWritebackInstruction()
1882 Inst.setOpcode(ARM::RFEDB); in DecodeMemMultipleWritebackInstruction()
1884 case ARM::LDMDB_UPD: in DecodeMemMultipleWritebackInstruction()
1885 Inst.setOpcode(ARM::RFEDB_UPD); in DecodeMemMultipleWritebackInstruction()
1887 case ARM::LDMIA: in DecodeMemMultipleWritebackInstruction()
1888 Inst.setOpcode(ARM::RFEIA); in DecodeMemMultipleWritebackInstruction()
1890 case ARM::LDMIA_UPD: in DecodeMemMultipleWritebackInstruction()
1891 Inst.setOpcode(ARM::RFEIA_UPD); in DecodeMemMultipleWritebackInstruction()
1893 case ARM::LDMIB: in DecodeMemMultipleWritebackInstruction()
1894 Inst.setOpcode(ARM::RFEIB); in DecodeMemMultipleWritebackInstruction()
1896 case ARM::LDMIB_UPD: in DecodeMemMultipleWritebackInstruction()
1897 Inst.setOpcode(ARM::RFEIB_UPD); in DecodeMemMultipleWritebackInstruction()
1899 case ARM::STMDA: in DecodeMemMultipleWritebackInstruction()
1900 Inst.setOpcode(ARM::SRSDA); in DecodeMemMultipleWritebackInstruction()
1902 case ARM::STMDA_UPD: in DecodeMemMultipleWritebackInstruction()
1903 Inst.setOpcode(ARM::SRSDA_UPD); in DecodeMemMultipleWritebackInstruction()
1905 case ARM::STMDB: in DecodeMemMultipleWritebackInstruction()
1906 Inst.setOpcode(ARM::SRSDB); in DecodeMemMultipleWritebackInstruction()
1908 case ARM::STMDB_UPD: in DecodeMemMultipleWritebackInstruction()
1909 Inst.setOpcode(ARM::SRSDB_UPD); in DecodeMemMultipleWritebackInstruction()
1911 case ARM::STMIA: in DecodeMemMultipleWritebackInstruction()
1912 Inst.setOpcode(ARM::SRSIA); in DecodeMemMultipleWritebackInstruction()
1914 case ARM::STMIA_UPD: in DecodeMemMultipleWritebackInstruction()
1915 Inst.setOpcode(ARM::SRSIA_UPD); in DecodeMemMultipleWritebackInstruction()
1917 case ARM::STMIB: in DecodeMemMultipleWritebackInstruction()
1918 Inst.setOpcode(ARM::SRSIB); in DecodeMemMultipleWritebackInstruction()
1920 case ARM::STMIB_UPD: in DecodeMemMultipleWritebackInstruction()
1921 Inst.setOpcode(ARM::SRSIB_UPD); in DecodeMemMultipleWritebackInstruction()
1971 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) in DecodeHINTInstruction()
2001 Inst.setOpcode(ARM::CPS3p); in DecodeCPSInstruction()
2006 Inst.setOpcode(ARM::CPS2p); in DecodeCPSInstruction()
2011 Inst.setOpcode(ARM::CPS1p); in DecodeCPSInstruction()
2016 Inst.setOpcode(ARM::CPS1p); in DecodeCPSInstruction()
2041 Inst.setOpcode(ARM::t2CPS3p); in DecodeT2CPSInstruction()
2046 Inst.setOpcode(ARM::t2CPS2p); in DecodeT2CPSInstruction()
2051 Inst.setOpcode(ARM::t2CPS1p); in DecodeT2CPSInstruction()
2059 Inst.setOpcode(ARM::t2HINT); in DecodeT2CPSInstruction()
2078 if (Inst.getOpcode() == ARM::t2MOVTi16) in DecodeT2MOVTWInstruction()
2101 if (Inst.getOpcode() == ARM::MOVTi16) in DecodeArmMOVTWInstruction()
2175 if (!FeatureBits[ARM::HasV8_1aOps] || in DecodeSETPANInstruction()
2176 !FeatureBits[ARM::HasV8Ops]) in DecodeSETPANInstruction()
2188 Inst.setOpcode(ARM::SETPAN); in DecodeSETPANInstruction()
2295 Inst.setOpcode(ARM::BLXi); in DecodeBranchImmInstruction()
2343 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: in DecodeVLDInstruction()
2344 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: in DecodeVLDInstruction()
2345 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: in DecodeVLDInstruction()
2346 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: in DecodeVLDInstruction()
2347 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: in DecodeVLDInstruction()
2348 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: in DecodeVLDInstruction()
2349 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: in DecodeVLDInstruction()
2350 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: in DecodeVLDInstruction()
2351 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: in DecodeVLDInstruction()
2355 case ARM::VLD2b16: in DecodeVLDInstruction()
2356 case ARM::VLD2b32: in DecodeVLDInstruction()
2357 case ARM::VLD2b8: in DecodeVLDInstruction()
2358 case ARM::VLD2b16wb_fixed: in DecodeVLDInstruction()
2359 case ARM::VLD2b16wb_register: in DecodeVLDInstruction()
2360 case ARM::VLD2b32wb_fixed: in DecodeVLDInstruction()
2361 case ARM::VLD2b32wb_register: in DecodeVLDInstruction()
2362 case ARM::VLD2b8wb_fixed: in DecodeVLDInstruction()
2363 case ARM::VLD2b8wb_register: in DecodeVLDInstruction()
2374 case ARM::VLD3d8: in DecodeVLDInstruction()
2375 case ARM::VLD3d16: in DecodeVLDInstruction()
2376 case ARM::VLD3d32: in DecodeVLDInstruction()
2377 case ARM::VLD3d8_UPD: in DecodeVLDInstruction()
2378 case ARM::VLD3d16_UPD: in DecodeVLDInstruction()
2379 case ARM::VLD3d32_UPD: in DecodeVLDInstruction()
2380 case ARM::VLD4d8: in DecodeVLDInstruction()
2381 case ARM::VLD4d16: in DecodeVLDInstruction()
2382 case ARM::VLD4d32: in DecodeVLDInstruction()
2383 case ARM::VLD4d8_UPD: in DecodeVLDInstruction()
2384 case ARM::VLD4d16_UPD: in DecodeVLDInstruction()
2385 case ARM::VLD4d32_UPD: in DecodeVLDInstruction()
2389 case ARM::VLD3q8: in DecodeVLDInstruction()
2390 case ARM::VLD3q16: in DecodeVLDInstruction()
2391 case ARM::VLD3q32: in DecodeVLDInstruction()
2392 case ARM::VLD3q8_UPD: in DecodeVLDInstruction()
2393 case ARM::VLD3q16_UPD: in DecodeVLDInstruction()
2394 case ARM::VLD3q32_UPD: in DecodeVLDInstruction()
2395 case ARM::VLD4q8: in DecodeVLDInstruction()
2396 case ARM::VLD4q16: in DecodeVLDInstruction()
2397 case ARM::VLD4q32: in DecodeVLDInstruction()
2398 case ARM::VLD4q8_UPD: in DecodeVLDInstruction()
2399 case ARM::VLD4q16_UPD: in DecodeVLDInstruction()
2400 case ARM::VLD4q32_UPD: in DecodeVLDInstruction()
2409 case ARM::VLD3d8: in DecodeVLDInstruction()
2410 case ARM::VLD3d16: in DecodeVLDInstruction()
2411 case ARM::VLD3d32: in DecodeVLDInstruction()
2412 case ARM::VLD3d8_UPD: in DecodeVLDInstruction()
2413 case ARM::VLD3d16_UPD: in DecodeVLDInstruction()
2414 case ARM::VLD3d32_UPD: in DecodeVLDInstruction()
2415 case ARM::VLD4d8: in DecodeVLDInstruction()
2416 case ARM::VLD4d16: in DecodeVLDInstruction()
2417 case ARM::VLD4d32: in DecodeVLDInstruction()
2418 case ARM::VLD4d8_UPD: in DecodeVLDInstruction()
2419 case ARM::VLD4d16_UPD: in DecodeVLDInstruction()
2420 case ARM::VLD4d32_UPD: in DecodeVLDInstruction()
2424 case ARM::VLD3q8: in DecodeVLDInstruction()
2425 case ARM::VLD3q16: in DecodeVLDInstruction()
2426 case ARM::VLD3q32: in DecodeVLDInstruction()
2427 case ARM::VLD3q8_UPD: in DecodeVLDInstruction()
2428 case ARM::VLD3q16_UPD: in DecodeVLDInstruction()
2429 case ARM::VLD3q32_UPD: in DecodeVLDInstruction()
2430 case ARM::VLD4q8: in DecodeVLDInstruction()
2431 case ARM::VLD4q16: in DecodeVLDInstruction()
2432 case ARM::VLD4q32: in DecodeVLDInstruction()
2433 case ARM::VLD4q8_UPD: in DecodeVLDInstruction()
2434 case ARM::VLD4q16_UPD: in DecodeVLDInstruction()
2435 case ARM::VLD4q32_UPD: in DecodeVLDInstruction()
2445 case ARM::VLD4d8: in DecodeVLDInstruction()
2446 case ARM::VLD4d16: in DecodeVLDInstruction()
2447 case ARM::VLD4d32: in DecodeVLDInstruction()
2448 case ARM::VLD4d8_UPD: in DecodeVLDInstruction()
2449 case ARM::VLD4d16_UPD: in DecodeVLDInstruction()
2450 case ARM::VLD4d32_UPD: in DecodeVLDInstruction()
2454 case ARM::VLD4q8: in DecodeVLDInstruction()
2455 case ARM::VLD4q16: in DecodeVLDInstruction()
2456 case ARM::VLD4q32: in DecodeVLDInstruction()
2457 case ARM::VLD4q8_UPD: in DecodeVLDInstruction()
2458 case ARM::VLD4q16_UPD: in DecodeVLDInstruction()
2459 case ARM::VLD4q32_UPD: in DecodeVLDInstruction()
2469 case ARM::VLD1d8wb_fixed: in DecodeVLDInstruction()
2470 case ARM::VLD1d16wb_fixed: in DecodeVLDInstruction()
2471 case ARM::VLD1d32wb_fixed: in DecodeVLDInstruction()
2472 case ARM::VLD1d64wb_fixed: in DecodeVLDInstruction()
2473 case ARM::VLD1d8wb_register: in DecodeVLDInstruction()
2474 case ARM::VLD1d16wb_register: in DecodeVLDInstruction()
2475 case ARM::VLD1d32wb_register: in DecodeVLDInstruction()
2476 case ARM::VLD1d64wb_register: in DecodeVLDInstruction()
2477 case ARM::VLD1q8wb_fixed: in DecodeVLDInstruction()
2478 case ARM::VLD1q16wb_fixed: in DecodeVLDInstruction()
2479 case ARM::VLD1q32wb_fixed: in DecodeVLDInstruction()
2480 case ARM::VLD1q64wb_fixed: in DecodeVLDInstruction()
2481 case ARM::VLD1q8wb_register: in DecodeVLDInstruction()
2482 case ARM::VLD1q16wb_register: in DecodeVLDInstruction()
2483 case ARM::VLD1q32wb_register: in DecodeVLDInstruction()
2484 case ARM::VLD1q64wb_register: in DecodeVLDInstruction()
2485 case ARM::VLD1d8Twb_fixed: in DecodeVLDInstruction()
2486 case ARM::VLD1d8Twb_register: in DecodeVLDInstruction()
2487 case ARM::VLD1d16Twb_fixed: in DecodeVLDInstruction()
2488 case ARM::VLD1d16Twb_register: in DecodeVLDInstruction()
2489 case ARM::VLD1d32Twb_fixed: in DecodeVLDInstruction()
2490 case ARM::VLD1d32Twb_register: in DecodeVLDInstruction()
2491 case ARM::VLD1d64Twb_fixed: in DecodeVLDInstruction()
2492 case ARM::VLD1d64Twb_register: in DecodeVLDInstruction()
2493 case ARM::VLD1d8Qwb_fixed: in DecodeVLDInstruction()
2494 case ARM::VLD1d8Qwb_register: in DecodeVLDInstruction()
2495 case ARM::VLD1d16Qwb_fixed: in DecodeVLDInstruction()
2496 case ARM::VLD1d16Qwb_register: in DecodeVLDInstruction()
2497 case ARM::VLD1d32Qwb_fixed: in DecodeVLDInstruction()
2498 case ARM::VLD1d32Qwb_register: in DecodeVLDInstruction()
2499 case ARM::VLD1d64Qwb_fixed: in DecodeVLDInstruction()
2500 case ARM::VLD1d64Qwb_register: in DecodeVLDInstruction()
2501 case ARM::VLD2d8wb_fixed: in DecodeVLDInstruction()
2502 case ARM::VLD2d16wb_fixed: in DecodeVLDInstruction()
2503 case ARM::VLD2d32wb_fixed: in DecodeVLDInstruction()
2504 case ARM::VLD2q8wb_fixed: in DecodeVLDInstruction()
2505 case ARM::VLD2q16wb_fixed: in DecodeVLDInstruction()
2506 case ARM::VLD2q32wb_fixed: in DecodeVLDInstruction()
2507 case ARM::VLD2d8wb_register: in DecodeVLDInstruction()
2508 case ARM::VLD2d16wb_register: in DecodeVLDInstruction()
2509 case ARM::VLD2d32wb_register: in DecodeVLDInstruction()
2510 case ARM::VLD2q8wb_register: in DecodeVLDInstruction()
2511 case ARM::VLD2q16wb_register: in DecodeVLDInstruction()
2512 case ARM::VLD2q32wb_register: in DecodeVLDInstruction()
2513 case ARM::VLD2b8wb_fixed: in DecodeVLDInstruction()
2514 case ARM::VLD2b16wb_fixed: in DecodeVLDInstruction()
2515 case ARM::VLD2b32wb_fixed: in DecodeVLDInstruction()
2516 case ARM::VLD2b8wb_register: in DecodeVLDInstruction()
2517 case ARM::VLD2b16wb_register: in DecodeVLDInstruction()
2518 case ARM::VLD2b32wb_register: in DecodeVLDInstruction()
2521 case ARM::VLD3d8_UPD: in DecodeVLDInstruction()
2522 case ARM::VLD3d16_UPD: in DecodeVLDInstruction()
2523 case ARM::VLD3d32_UPD: in DecodeVLDInstruction()
2524 case ARM::VLD3q8_UPD: in DecodeVLDInstruction()
2525 case ARM::VLD3q16_UPD: in DecodeVLDInstruction()
2526 case ARM::VLD3q32_UPD: in DecodeVLDInstruction()
2527 case ARM::VLD4d8_UPD: in DecodeVLDInstruction()
2528 case ARM::VLD4d16_UPD: in DecodeVLDInstruction()
2529 case ARM::VLD4d32_UPD: in DecodeVLDInstruction()
2530 case ARM::VLD4q8_UPD: in DecodeVLDInstruction()
2531 case ARM::VLD4q16_UPD: in DecodeVLDInstruction()
2532 case ARM::VLD4q32_UPD: in DecodeVLDInstruction()
2558 case ARM::VLD1d8wb_fixed: in DecodeVLDInstruction()
2559 case ARM::VLD1d16wb_fixed: in DecodeVLDInstruction()
2560 case ARM::VLD1d32wb_fixed: in DecodeVLDInstruction()
2561 case ARM::VLD1d64wb_fixed: in DecodeVLDInstruction()
2562 case ARM::VLD1d8Twb_fixed: in DecodeVLDInstruction()
2563 case ARM::VLD1d16Twb_fixed: in DecodeVLDInstruction()
2564 case ARM::VLD1d32Twb_fixed: in DecodeVLDInstruction()
2565 case ARM::VLD1d64Twb_fixed: in DecodeVLDInstruction()
2566 case ARM::VLD1d8Qwb_fixed: in DecodeVLDInstruction()
2567 case ARM::VLD1d16Qwb_fixed: in DecodeVLDInstruction()
2568 case ARM::VLD1d32Qwb_fixed: in DecodeVLDInstruction()
2569 case ARM::VLD1d64Qwb_fixed: in DecodeVLDInstruction()
2570 case ARM::VLD1d8wb_register: in DecodeVLDInstruction()
2571 case ARM::VLD1d16wb_register: in DecodeVLDInstruction()
2572 case ARM::VLD1d32wb_register: in DecodeVLDInstruction()
2573 case ARM::VLD1d64wb_register: in DecodeVLDInstruction()
2574 case ARM::VLD1q8wb_fixed: in DecodeVLDInstruction()
2575 case ARM::VLD1q16wb_fixed: in DecodeVLDInstruction()
2576 case ARM::VLD1q32wb_fixed: in DecodeVLDInstruction()
2577 case ARM::VLD1q64wb_fixed: in DecodeVLDInstruction()
2578 case ARM::VLD1q8wb_register: in DecodeVLDInstruction()
2579 case ARM::VLD1q16wb_register: in DecodeVLDInstruction()
2580 case ARM::VLD1q32wb_register: in DecodeVLDInstruction()
2581 case ARM::VLD1q64wb_register: in DecodeVLDInstruction()
2589 case ARM::VLD2d8wb_fixed: in DecodeVLDInstruction()
2590 case ARM::VLD2d16wb_fixed: in DecodeVLDInstruction()
2591 case ARM::VLD2d32wb_fixed: in DecodeVLDInstruction()
2592 case ARM::VLD2b8wb_fixed: in DecodeVLDInstruction()
2593 case ARM::VLD2b16wb_fixed: in DecodeVLDInstruction()
2594 case ARM::VLD2b32wb_fixed: in DecodeVLDInstruction()
2595 case ARM::VLD2q8wb_fixed: in DecodeVLDInstruction()
2596 case ARM::VLD2q16wb_fixed: in DecodeVLDInstruction()
2597 case ARM::VLD2q32wb_fixed: in DecodeVLDInstruction()
2668 case ARM::VST1d8wb_fixed: in DecodeVSTInstruction()
2669 case ARM::VST1d16wb_fixed: in DecodeVSTInstruction()
2670 case ARM::VST1d32wb_fixed: in DecodeVSTInstruction()
2671 case ARM::VST1d64wb_fixed: in DecodeVSTInstruction()
2672 case ARM::VST1d8wb_register: in DecodeVSTInstruction()
2673 case ARM::VST1d16wb_register: in DecodeVSTInstruction()
2674 case ARM::VST1d32wb_register: in DecodeVSTInstruction()
2675 case ARM::VST1d64wb_register: in DecodeVSTInstruction()
2676 case ARM::VST1q8wb_fixed: in DecodeVSTInstruction()
2677 case ARM::VST1q16wb_fixed: in DecodeVSTInstruction()
2678 case ARM::VST1q32wb_fixed: in DecodeVSTInstruction()
2679 case ARM::VST1q64wb_fixed: in DecodeVSTInstruction()
2680 case ARM::VST1q8wb_register: in DecodeVSTInstruction()
2681 case ARM::VST1q16wb_register: in DecodeVSTInstruction()
2682 case ARM::VST1q32wb_register: in DecodeVSTInstruction()
2683 case ARM::VST1q64wb_register: in DecodeVSTInstruction()
2684 case ARM::VST1d8Twb_fixed: in DecodeVSTInstruction()
2685 case ARM::VST1d16Twb_fixed: in DecodeVSTInstruction()
2686 case ARM::VST1d32Twb_fixed: in DecodeVSTInstruction()
2687 case ARM::VST1d64Twb_fixed: in DecodeVSTInstruction()
2688 case ARM::VST1d8Twb_register: in DecodeVSTInstruction()
2689 case ARM::VST1d16Twb_register: in DecodeVSTInstruction()
2690 case ARM::VST1d32Twb_register: in DecodeVSTInstruction()
2691 case ARM::VST1d64Twb_register: in DecodeVSTInstruction()
2692 case ARM::VST1d8Qwb_fixed: in DecodeVSTInstruction()
2693 case ARM::VST1d16Qwb_fixed: in DecodeVSTInstruction()
2694 case ARM::VST1d32Qwb_fixed: in DecodeVSTInstruction()
2695 case ARM::VST1d64Qwb_fixed: in DecodeVSTInstruction()
2696 case ARM::VST1d8Qwb_register: in DecodeVSTInstruction()
2697 case ARM::VST1d16Qwb_register: in DecodeVSTInstruction()
2698 case ARM::VST1d32Qwb_register: in DecodeVSTInstruction()
2699 case ARM::VST1d64Qwb_register: in DecodeVSTInstruction()
2700 case ARM::VST2d8wb_fixed: in DecodeVSTInstruction()
2701 case ARM::VST2d16wb_fixed: in DecodeVSTInstruction()
2702 case ARM::VST2d32wb_fixed: in DecodeVSTInstruction()
2703 case ARM::VST2d8wb_register: in DecodeVSTInstruction()
2704 case ARM::VST2d16wb_register: in DecodeVSTInstruction()
2705 case ARM::VST2d32wb_register: in DecodeVSTInstruction()
2706 case ARM::VST2q8wb_fixed: in DecodeVSTInstruction()
2707 case ARM::VST2q16wb_fixed: in DecodeVSTInstruction()
2708 case ARM::VST2q32wb_fixed: in DecodeVSTInstruction()
2709 case ARM::VST2q8wb_register: in DecodeVSTInstruction()
2710 case ARM::VST2q16wb_register: in DecodeVSTInstruction()
2711 case ARM::VST2q32wb_register: in DecodeVSTInstruction()
2712 case ARM::VST2b8wb_fixed: in DecodeVSTInstruction()
2713 case ARM::VST2b16wb_fixed: in DecodeVSTInstruction()
2714 case ARM::VST2b32wb_fixed: in DecodeVSTInstruction()
2715 case ARM::VST2b8wb_register: in DecodeVSTInstruction()
2716 case ARM::VST2b16wb_register: in DecodeVSTInstruction()
2717 case ARM::VST2b32wb_register: in DecodeVSTInstruction()
2722 case ARM::VST3d8_UPD: in DecodeVSTInstruction()
2723 case ARM::VST3d16_UPD: in DecodeVSTInstruction()
2724 case ARM::VST3d32_UPD: in DecodeVSTInstruction()
2725 case ARM::VST3q8_UPD: in DecodeVSTInstruction()
2726 case ARM::VST3q16_UPD: in DecodeVSTInstruction()
2727 case ARM::VST3q32_UPD: in DecodeVSTInstruction()
2728 case ARM::VST4d8_UPD: in DecodeVSTInstruction()
2729 case ARM::VST4d16_UPD: in DecodeVSTInstruction()
2730 case ARM::VST4d32_UPD: in DecodeVSTInstruction()
2731 case ARM::VST4q8_UPD: in DecodeVSTInstruction()
2732 case ARM::VST4q16_UPD: in DecodeVSTInstruction()
2733 case ARM::VST4q32_UPD: in DecodeVSTInstruction()
2755 case ARM::VST1d8wb_fixed: in DecodeVSTInstruction()
2756 case ARM::VST1d16wb_fixed: in DecodeVSTInstruction()
2757 case ARM::VST1d32wb_fixed: in DecodeVSTInstruction()
2758 case ARM::VST1d64wb_fixed: in DecodeVSTInstruction()
2759 case ARM::VST1q8wb_fixed: in DecodeVSTInstruction()
2760 case ARM::VST1q16wb_fixed: in DecodeVSTInstruction()
2761 case ARM::VST1q32wb_fixed: in DecodeVSTInstruction()
2762 case ARM::VST1q64wb_fixed: in DecodeVSTInstruction()
2763 case ARM::VST1d8Twb_fixed: in DecodeVSTInstruction()
2764 case ARM::VST1d16Twb_fixed: in DecodeVSTInstruction()
2765 case ARM::VST1d32Twb_fixed: in DecodeVSTInstruction()
2766 case ARM::VST1d64Twb_fixed: in DecodeVSTInstruction()
2767 case ARM::VST1d8Qwb_fixed: in DecodeVSTInstruction()
2768 case ARM::VST1d16Qwb_fixed: in DecodeVSTInstruction()
2769 case ARM::VST1d32Qwb_fixed: in DecodeVSTInstruction()
2770 case ARM::VST1d64Qwb_fixed: in DecodeVSTInstruction()
2771 case ARM::VST2d8wb_fixed: in DecodeVSTInstruction()
2772 case ARM::VST2d16wb_fixed: in DecodeVSTInstruction()
2773 case ARM::VST2d32wb_fixed: in DecodeVSTInstruction()
2774 case ARM::VST2q8wb_fixed: in DecodeVSTInstruction()
2775 case ARM::VST2q16wb_fixed: in DecodeVSTInstruction()
2776 case ARM::VST2q32wb_fixed: in DecodeVSTInstruction()
2777 case ARM::VST2b8wb_fixed: in DecodeVSTInstruction()
2778 case ARM::VST2b16wb_fixed: in DecodeVSTInstruction()
2779 case ARM::VST2b32wb_fixed: in DecodeVSTInstruction()
2786 case ARM::VST1q16: in DecodeVSTInstruction()
2787 case ARM::VST1q32: in DecodeVSTInstruction()
2788 case ARM::VST1q64: in DecodeVSTInstruction()
2789 case ARM::VST1q8: in DecodeVSTInstruction()
2790 case ARM::VST1q16wb_fixed: in DecodeVSTInstruction()
2791 case ARM::VST1q16wb_register: in DecodeVSTInstruction()
2792 case ARM::VST1q32wb_fixed: in DecodeVSTInstruction()
2793 case ARM::VST1q32wb_register: in DecodeVSTInstruction()
2794 case ARM::VST1q64wb_fixed: in DecodeVSTInstruction()
2795 case ARM::VST1q64wb_register: in DecodeVSTInstruction()
2796 case ARM::VST1q8wb_fixed: in DecodeVSTInstruction()
2797 case ARM::VST1q8wb_register: in DecodeVSTInstruction()
2798 case ARM::VST2d16: in DecodeVSTInstruction()
2799 case ARM::VST2d32: in DecodeVSTInstruction()
2800 case ARM::VST2d8: in DecodeVSTInstruction()
2801 case ARM::VST2d16wb_fixed: in DecodeVSTInstruction()
2802 case ARM::VST2d16wb_register: in DecodeVSTInstruction()
2803 case ARM::VST2d32wb_fixed: in DecodeVSTInstruction()
2804 case ARM::VST2d32wb_register: in DecodeVSTInstruction()
2805 case ARM::VST2d8wb_fixed: in DecodeVSTInstruction()
2806 case ARM::VST2d8wb_register: in DecodeVSTInstruction()
2810 case ARM::VST2b16: in DecodeVSTInstruction()
2811 case ARM::VST2b32: in DecodeVSTInstruction()
2812 case ARM::VST2b8: in DecodeVSTInstruction()
2813 case ARM::VST2b16wb_fixed: in DecodeVSTInstruction()
2814 case ARM::VST2b16wb_register: in DecodeVSTInstruction()
2815 case ARM::VST2b32wb_fixed: in DecodeVSTInstruction()
2816 case ARM::VST2b32wb_register: in DecodeVSTInstruction()
2817 case ARM::VST2b8wb_fixed: in DecodeVSTInstruction()
2818 case ARM::VST2b8wb_register: in DecodeVSTInstruction()
2829 case ARM::VST3d8: in DecodeVSTInstruction()
2830 case ARM::VST3d16: in DecodeVSTInstruction()
2831 case ARM::VST3d32: in DecodeVSTInstruction()
2832 case ARM::VST3d8_UPD: in DecodeVSTInstruction()
2833 case ARM::VST3d16_UPD: in DecodeVSTInstruction()
2834 case ARM::VST3d32_UPD: in DecodeVSTInstruction()
2835 case ARM::VST4d8: in DecodeVSTInstruction()
2836 case ARM::VST4d16: in DecodeVSTInstruction()
2837 case ARM::VST4d32: in DecodeVSTInstruction()
2838 case ARM::VST4d8_UPD: in DecodeVSTInstruction()
2839 case ARM::VST4d16_UPD: in DecodeVSTInstruction()
2840 case ARM::VST4d32_UPD: in DecodeVSTInstruction()
2844 case ARM::VST3q8: in DecodeVSTInstruction()
2845 case ARM::VST3q16: in DecodeVSTInstruction()
2846 case ARM::VST3q32: in DecodeVSTInstruction()
2847 case ARM::VST3q8_UPD: in DecodeVSTInstruction()
2848 case ARM::VST3q16_UPD: in DecodeVSTInstruction()
2849 case ARM::VST3q32_UPD: in DecodeVSTInstruction()
2850 case ARM::VST4q8: in DecodeVSTInstruction()
2851 case ARM::VST4q16: in DecodeVSTInstruction()
2852 case ARM::VST4q32: in DecodeVSTInstruction()
2853 case ARM::VST4q8_UPD: in DecodeVSTInstruction()
2854 case ARM::VST4q16_UPD: in DecodeVSTInstruction()
2855 case ARM::VST4q32_UPD: in DecodeVSTInstruction()
2865 case ARM::VST3d8: in DecodeVSTInstruction()
2866 case ARM::VST3d16: in DecodeVSTInstruction()
2867 case ARM::VST3d32: in DecodeVSTInstruction()
2868 case ARM::VST3d8_UPD: in DecodeVSTInstruction()
2869 case ARM::VST3d16_UPD: in DecodeVSTInstruction()
2870 case ARM::VST3d32_UPD: in DecodeVSTInstruction()
2871 case ARM::VST4d8: in DecodeVSTInstruction()
2872 case ARM::VST4d16: in DecodeVSTInstruction()
2873 case ARM::VST4d32: in DecodeVSTInstruction()
2874 case ARM::VST4d8_UPD: in DecodeVSTInstruction()
2875 case ARM::VST4d16_UPD: in DecodeVSTInstruction()
2876 case ARM::VST4d32_UPD: in DecodeVSTInstruction()
2880 case ARM::VST3q8: in DecodeVSTInstruction()
2881 case ARM::VST3q16: in DecodeVSTInstruction()
2882 case ARM::VST3q32: in DecodeVSTInstruction()
2883 case ARM::VST3q8_UPD: in DecodeVSTInstruction()
2884 case ARM::VST3q16_UPD: in DecodeVSTInstruction()
2885 case ARM::VST3q32_UPD: in DecodeVSTInstruction()
2886 case ARM::VST4q8: in DecodeVSTInstruction()
2887 case ARM::VST4q16: in DecodeVSTInstruction()
2888 case ARM::VST4q32: in DecodeVSTInstruction()
2889 case ARM::VST4q8_UPD: in DecodeVSTInstruction()
2890 case ARM::VST4q16_UPD: in DecodeVSTInstruction()
2891 case ARM::VST4q32_UPD: in DecodeVSTInstruction()
2901 case ARM::VST4d8: in DecodeVSTInstruction()
2902 case ARM::VST4d16: in DecodeVSTInstruction()
2903 case ARM::VST4d32: in DecodeVSTInstruction()
2904 case ARM::VST4d8_UPD: in DecodeVSTInstruction()
2905 case ARM::VST4d16_UPD: in DecodeVSTInstruction()
2906 case ARM::VST4d32_UPD: in DecodeVSTInstruction()
2910 case ARM::VST4q8: in DecodeVSTInstruction()
2911 case ARM::VST4q16: in DecodeVSTInstruction()
2912 case ARM::VST4q32: in DecodeVSTInstruction()
2913 case ARM::VST4q8_UPD: in DecodeVSTInstruction()
2914 case ARM::VST4q16_UPD: in DecodeVSTInstruction()
2915 case ARM::VST4q32_UPD: in DecodeVSTInstruction()
2942 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: in DecodeVLD1DupInstruction()
2943 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: in DecodeVLD1DupInstruction()
2944 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: in DecodeVLD1DupInstruction()
2945 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: in DecodeVLD1DupInstruction()
2986 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: in DecodeVLD2DupInstruction()
2987 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: in DecodeVLD2DupInstruction()
2988 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: in DecodeVLD2DupInstruction()
2989 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: in DecodeVLD2DupInstruction()
2993 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: in DecodeVLD2DupInstruction()
2994 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: in DecodeVLD2DupInstruction()
2995 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: in DecodeVLD2DupInstruction()
2996 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: in DecodeVLD2DupInstruction()
3133 case ARM::VORRiv4i16: in DecodeNEONModImmInstruction()
3134 case ARM::VORRiv2i32: in DecodeNEONModImmInstruction()
3135 case ARM::VBICiv4i16: in DecodeNEONModImmInstruction()
3136 case ARM::VBICiv2i32: in DecodeNEONModImmInstruction()
3140 case ARM::VORRiv8i16: in DecodeNEONModImmInstruction()
3141 case ARM::VORRiv4i32: in DecodeNEONModImmInstruction()
3142 case ARM::VBICiv8i16: in DecodeNEONModImmInstruction()
3143 case ARM::VBICiv4i32: in DecodeNEONModImmInstruction()
3217 case ARM::VTBL2: in DecodeTBLInstruction()
3218 case ARM::VTBX2: in DecodeTBLInstruction()
3246 case ARM::tADR: in DecodeThumbAddSpecialReg()
3248 case ARM::tADDrSPi: in DecodeThumbAddSpecialReg()
3249 Inst.addOperand(MCOperand::createReg(ARM::SP)); in DecodeThumbAddSpecialReg()
3322 Inst.addOperand(MCOperand::createReg(ARM::SP)); in DecodeThumbAddrModeSP()
3338 case ARM::t2STRHs: in DecodeT2AddrModeSOReg()
3339 case ARM::t2STRBs: in DecodeT2AddrModeSOReg()
3340 case ARM::t2STRs: in DecodeT2AddrModeSOReg()
3366 bool hasMP = featureBits[ARM::FeatureMP]; in DecodeT2LoadShift()
3367 bool hasV7Ops = featureBits[ARM::HasV7Ops]; in DecodeT2LoadShift()
3371 case ARM::t2LDRBs: in DecodeT2LoadShift()
3372 Inst.setOpcode(ARM::t2LDRBpci); in DecodeT2LoadShift()
3374 case ARM::t2LDRHs: in DecodeT2LoadShift()
3375 Inst.setOpcode(ARM::t2LDRHpci); in DecodeT2LoadShift()
3377 case ARM::t2LDRSHs: in DecodeT2LoadShift()
3378 Inst.setOpcode(ARM::t2LDRSHpci); in DecodeT2LoadShift()
3380 case ARM::t2LDRSBs: in DecodeT2LoadShift()
3381 Inst.setOpcode(ARM::t2LDRSBpci); in DecodeT2LoadShift()
3383 case ARM::t2LDRs: in DecodeT2LoadShift()
3384 Inst.setOpcode(ARM::t2LDRpci); in DecodeT2LoadShift()
3386 case ARM::t2PLDs: in DecodeT2LoadShift()
3387 Inst.setOpcode(ARM::t2PLDpci); in DecodeT2LoadShift()
3389 case ARM::t2PLIs: in DecodeT2LoadShift()
3390 Inst.setOpcode(ARM::t2PLIpci); in DecodeT2LoadShift()
3401 case ARM::t2LDRSHs: in DecodeT2LoadShift()
3403 case ARM::t2LDRHs: in DecodeT2LoadShift()
3404 Inst.setOpcode(ARM::t2PLDWs); in DecodeT2LoadShift()
3406 case ARM::t2LDRSBs: in DecodeT2LoadShift()
3407 Inst.setOpcode(ARM::t2PLIs); in DecodeT2LoadShift()
3414 case ARM::t2PLDs: in DecodeT2LoadShift()
3416 case ARM::t2PLIs: in DecodeT2LoadShift()
3420 case ARM::t2PLDWs: in DecodeT2LoadShift()
3453 bool hasMP = featureBits[ARM::FeatureMP]; in DecodeT2LoadImm8()
3454 bool hasV7Ops = featureBits[ARM::HasV7Ops]; in DecodeT2LoadImm8()
3458 case ARM::t2LDRi8: in DecodeT2LoadImm8()
3459 Inst.setOpcode(ARM::t2LDRpci); in DecodeT2LoadImm8()
3461 case ARM::t2LDRBi8: in DecodeT2LoadImm8()
3462 Inst.setOpcode(ARM::t2LDRBpci); in DecodeT2LoadImm8()
3464 case ARM::t2LDRSBi8: in DecodeT2LoadImm8()
3465 Inst.setOpcode(ARM::t2LDRSBpci); in DecodeT2LoadImm8()
3467 case ARM::t2LDRHi8: in DecodeT2LoadImm8()
3468 Inst.setOpcode(ARM::t2LDRHpci); in DecodeT2LoadImm8()
3470 case ARM::t2LDRSHi8: in DecodeT2LoadImm8()
3471 Inst.setOpcode(ARM::t2LDRSHpci); in DecodeT2LoadImm8()
3473 case ARM::t2PLDi8: in DecodeT2LoadImm8()
3474 Inst.setOpcode(ARM::t2PLDpci); in DecodeT2LoadImm8()
3476 case ARM::t2PLIi8: in DecodeT2LoadImm8()
3477 Inst.setOpcode(ARM::t2PLIpci); in DecodeT2LoadImm8()
3487 case ARM::t2LDRSHi8: in DecodeT2LoadImm8()
3489 case ARM::t2LDRHi8: in DecodeT2LoadImm8()
3491 Inst.setOpcode(ARM::t2PLDWi8); in DecodeT2LoadImm8()
3493 case ARM::t2LDRSBi8: in DecodeT2LoadImm8()
3494 Inst.setOpcode(ARM::t2PLIi8); in DecodeT2LoadImm8()
3502 case ARM::t2PLDi8: in DecodeT2LoadImm8()
3504 case ARM::t2PLIi8: in DecodeT2LoadImm8()
3508 case ARM::t2PLDWi8: in DecodeT2LoadImm8()
3534 bool hasMP = featureBits[ARM::FeatureMP]; in DecodeT2LoadImm12()
3535 bool hasV7Ops = featureBits[ARM::HasV7Ops]; in DecodeT2LoadImm12()
3539 case ARM::t2LDRi12: in DecodeT2LoadImm12()
3540 Inst.setOpcode(ARM::t2LDRpci); in DecodeT2LoadImm12()
3542 case ARM::t2LDRHi12: in DecodeT2LoadImm12()
3543 Inst.setOpcode(ARM::t2LDRHpci); in DecodeT2LoadImm12()
3545 case ARM::t2LDRSHi12: in DecodeT2LoadImm12()
3546 Inst.setOpcode(ARM::t2LDRSHpci); in DecodeT2LoadImm12()
3548 case ARM::t2LDRBi12: in DecodeT2LoadImm12()
3549 Inst.setOpcode(ARM::t2LDRBpci); in DecodeT2LoadImm12()
3551 case ARM::t2LDRSBi12: in DecodeT2LoadImm12()
3552 Inst.setOpcode(ARM::t2LDRSBpci); in DecodeT2LoadImm12()
3554 case ARM::t2PLDi12: in DecodeT2LoadImm12()
3555 Inst.setOpcode(ARM::t2PLDpci); in DecodeT2LoadImm12()
3557 case ARM::t2PLIi12: in DecodeT2LoadImm12()
3558 Inst.setOpcode(ARM::t2PLIpci); in DecodeT2LoadImm12()
3568 case ARM::t2LDRSHi12: in DecodeT2LoadImm12()
3570 case ARM::t2LDRHi12: in DecodeT2LoadImm12()
3571 Inst.setOpcode(ARM::t2PLDWi12); in DecodeT2LoadImm12()
3573 case ARM::t2LDRSBi12: in DecodeT2LoadImm12()
3574 Inst.setOpcode(ARM::t2PLIi12); in DecodeT2LoadImm12()
3582 case ARM::t2PLDi12: in DecodeT2LoadImm12()
3584 case ARM::t2PLIi12: in DecodeT2LoadImm12()
3588 case ARM::t2PLDWi12: in DecodeT2LoadImm12()
3613 case ARM::t2LDRT: in DecodeT2LoadT()
3614 Inst.setOpcode(ARM::t2LDRpci); in DecodeT2LoadT()
3616 case ARM::t2LDRBT: in DecodeT2LoadT()
3617 Inst.setOpcode(ARM::t2LDRBpci); in DecodeT2LoadT()
3619 case ARM::t2LDRHT: in DecodeT2LoadT()
3620 Inst.setOpcode(ARM::t2LDRHpci); in DecodeT2LoadT()
3622 case ARM::t2LDRSBT: in DecodeT2LoadT()
3623 Inst.setOpcode(ARM::t2LDRSBpci); in DecodeT2LoadT()
3625 case ARM::t2LDRSHT: in DecodeT2LoadT()
3626 Inst.setOpcode(ARM::t2LDRSHpci); in DecodeT2LoadT()
3652 bool hasV7Ops = featureBits[ARM::HasV7Ops]; in DecodeT2LoadLabel()
3656 case ARM::t2LDRBpci: in DecodeT2LoadLabel()
3657 case ARM::t2LDRHpci: in DecodeT2LoadLabel()
3658 Inst.setOpcode(ARM::t2PLDpci); in DecodeT2LoadLabel()
3660 case ARM::t2LDRSBpci: in DecodeT2LoadLabel()
3661 Inst.setOpcode(ARM::t2PLIpci); in DecodeT2LoadLabel()
3663 case ARM::t2LDRSHpci: in DecodeT2LoadLabel()
3671 case ARM::t2PLDpci: in DecodeT2LoadLabel()
3673 case ARM::t2PLIpci: in DecodeT2LoadLabel()
3760 case ARM::t2STRT: in DecodeT2AddrModeImm8()
3761 case ARM::t2STRBT: in DecodeT2AddrModeImm8()
3762 case ARM::t2STRHT: in DecodeT2AddrModeImm8()
3763 case ARM::t2STRi8: in DecodeT2AddrModeImm8()
3764 case ARM::t2STRHi8: in DecodeT2AddrModeImm8()
3765 case ARM::t2STRBi8: in DecodeT2AddrModeImm8()
3775 case ARM::t2LDRT: in DecodeT2AddrModeImm8()
3776 case ARM::t2LDRBT: in DecodeT2AddrModeImm8()
3777 case ARM::t2LDRHT: in DecodeT2AddrModeImm8()
3778 case ARM::t2LDRSBT: in DecodeT2AddrModeImm8()
3779 case ARM::t2LDRSHT: in DecodeT2AddrModeImm8()
3780 case ARM::t2STRT: in DecodeT2AddrModeImm8()
3781 case ARM::t2STRBT: in DecodeT2AddrModeImm8()
3782 case ARM::t2STRHT: in DecodeT2AddrModeImm8()
3810 case ARM::t2LDR_PRE: in DecodeT2LdStPre()
3811 case ARM::t2LDR_POST: in DecodeT2LdStPre()
3812 Inst.setOpcode(ARM::t2LDRpci); in DecodeT2LdStPre()
3814 case ARM::t2LDRB_PRE: in DecodeT2LdStPre()
3815 case ARM::t2LDRB_POST: in DecodeT2LdStPre()
3816 Inst.setOpcode(ARM::t2LDRBpci); in DecodeT2LdStPre()
3818 case ARM::t2LDRH_PRE: in DecodeT2LdStPre()
3819 case ARM::t2LDRH_POST: in DecodeT2LdStPre()
3820 Inst.setOpcode(ARM::t2LDRHpci); in DecodeT2LdStPre()
3822 case ARM::t2LDRSB_PRE: in DecodeT2LdStPre()
3823 case ARM::t2LDRSB_POST: in DecodeT2LdStPre()
3825 Inst.setOpcode(ARM::t2PLIpci); in DecodeT2LdStPre()
3827 Inst.setOpcode(ARM::t2LDRSBpci); in DecodeT2LdStPre()
3829 case ARM::t2LDRSH_PRE: in DecodeT2LdStPre()
3830 case ARM::t2LDRSH_POST: in DecodeT2LdStPre()
3831 Inst.setOpcode(ARM::t2LDRSHpci); in DecodeT2LdStPre()
3867 case ARM::t2STRi12: in DecodeT2AddrModeImm12()
3868 case ARM::t2STRBi12: in DecodeT2AddrModeImm12()
3869 case ARM::t2STRHi12: in DecodeT2AddrModeImm12()
3888 Inst.addOperand(MCOperand::createReg(ARM::SP)); in DecodeThumbAddSPImm()
3889 Inst.addOperand(MCOperand::createReg(ARM::SP)); in DecodeThumbAddSPImm()
3899 if (Inst.getOpcode() == ARM::tADDrSP) { in DecodeThumbAddSPReg()
3905 Inst.addOperand(MCOperand::createReg(ARM::SP)); in DecodeThumbAddSPReg()
3908 } else if (Inst.getOpcode() == ARM::tADDspr) { in DecodeThumbAddSPReg()
3911 Inst.addOperand(MCOperand::createReg(ARM::SP)); in DecodeThumbAddSPReg()
3912 Inst.addOperand(MCOperand::createReg(ARM::SP)); in DecodeThumbAddSPReg()
3976 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15)) in DecodeCoprocessor()
3991 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; in DecodeThumbTableBranch()
4011 Inst.setOpcode(ARM::t2DSB); in DecodeThumb2BCCInstruction()
4014 Inst.setOpcode(ARM::t2DMB); in DecodeThumb2BCCInstruction()
4017 Inst.setOpcode(ARM::t2ISB); in DecodeThumb2BCCInstruction()
4129 if (FeatureBits[ARM::FeatureMClass]) { in DecodeMSRMask()
4149 if (!(FeatureBits[ARM::HasV7Ops])) in DecodeMSRMask()
4158 if (!(FeatureBits[ARM::HasV8MMainlineOps])) in DecodeMSRMask()
4168 if (!(FeatureBits[ARM::Feature8MSecExt])) in DecodeMSRMask()
4175 if (Inst.getOpcode() == ARM::t2MSR_M) { in DecodeMSRMask()
4177 if (!(FeatureBits[ARM::HasV7Ops])) { in DecodeMSRMask()
4191 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) in DecodeMSRMask()
5127 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; in DecodeVCVTD()
5143 Inst.setOpcode(ARM::VMOVv2f32); in DecodeVCVTD()
5148 Inst.setOpcode(ARM::VMOVv1i64); in DecodeVCVTD()
5150 Inst.setOpcode(ARM::VMOVv8i8); in DecodeVCVTD()
5155 Inst.setOpcode(ARM::VMVNv2i32); in DecodeVCVTD()
5157 Inst.setOpcode(ARM::VMOVv2i32); in DecodeVCVTD()
5162 Inst.setOpcode(ARM::VMVNv2i32); in DecodeVCVTD()
5164 Inst.setOpcode(ARM::VMOVv2i32); in DecodeVCVTD()
5186 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; in DecodeVCVTQ()
5202 Inst.setOpcode(ARM::VMOVv4f32); in DecodeVCVTQ()
5207 Inst.setOpcode(ARM::VMOVv2i64); in DecodeVCVTQ()
5209 Inst.setOpcode(ARM::VMOVv16i8); in DecodeVCVTQ()
5214 Inst.setOpcode(ARM::VMVNv4i32); in DecodeVCVTQ()
5216 Inst.setOpcode(ARM::VMOVv4i32); in DecodeVCVTQ()
5221 Inst.setOpcode(ARM::VMVNv4i32); in DecodeVCVTQ()
5223 Inst.setOpcode(ARM::VMOVv4i32); in DecodeVCVTQ()
5295 if (Inst.getOpcode() == ARM::MRRC2) { in DecoderForMRRC2AndMCRR2()
5303 if (Inst.getOpcode() == ARM::MCRR2) { in DecoderForMRRC2AndMCRR2()