Lines Matching refs:SEXTLOAD
142 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in X86TargetLowering()
695 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand); in X86TargetLowering()
794 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom); in X86TargetLowering()
795 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom); in X86TargetLowering()
796 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom); in X86TargetLowering()
907 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom); in X86TargetLowering()
908 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom); in X86TargetLowering()
909 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom); in X86TargetLowering()
913 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal); in X86TargetLowering()
914 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal); in X86TargetLowering()
915 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal); in X86TargetLowering()
916 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal); in X86TargetLowering()
917 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal); in X86TargetLowering()
918 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal); in X86TargetLowering()
1066 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal); in X86TargetLowering()
1067 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal); in X86TargetLowering()
1068 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal); in X86TargetLowering()
1069 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal); in X86TargetLowering()
1070 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal); in X86TargetLowering()
1071 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal); in X86TargetLowering()
1141 for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD, ISD::EXTLOAD}) { in X86TargetLowering()
1164 setLoadExtAction(ISD::SEXTLOAD, VT, MaskVT, Custom); in X86TargetLowering()
1513 for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD, ISD::EXTLOAD}) { in X86TargetLowering()
16346 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD) in LowerExtendedLoad()
16355 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget.hasInt256()) { in LowerExtendedLoad()
16420 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) && in LowerExtendedLoad()
16424 if (Ext == ISD::SEXTLOAD && RegSz >= 256) in LowerExtendedLoad()
16476 if (Ext == ISD::SEXTLOAD) { in LowerExtendedLoad()
28975 if (Mld->getExtensionType() != ISD::SEXTLOAD) in combineMaskedLoad()