Lines Matching refs:ADDR

5 ; CHECK-NEXT: mov    x[[ADDR:[0-9]+]], x0
7 ; CHECK-NEXT: ldaxr  [[RESULT:w[0-9]+]], [x[[ADDR]]]
10 ; CHECK-NEXT: stxr   [[SCRATCH_REG:w[0-9]+]], w2, [x[[ADDR]]]
42 ; CHECK-NEXT: mov    x[[ADDR:[0-9]+]], x0
44 ; CHECK-NEXT: ldaxr  [[RESULT:w[0-9]+]], [x[[ADDR]]
47 ; CHECK-NEXT: stlxr  [[SCRATCH_REG:w[0-9]+]], w2, [x[[ADDR]]
60 ; CHECK-NEXT: mov    x[[ADDR:[0-9]+]], x0
62 ; CHECK-NEXT: ldxr   [[RESULT:x[0-9]+]], [x[[ADDR]]]
65 ; CHECK-NEXT: stxr   [[SCRATCH_REG:w[0-9]+]], x2, [x[[ADDR]]]
92 ; CHECK: mov    x[[ADDR:[0-9]+]], x0
94 ; CHECK: ldaxr   x[[DEST_REG:[0-9]+]], [x[[ADDR]]]
97 ; CHECK: stlxr   [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x[[ADDR]]]
120 ; CHECK: mov    x[[ADDR:[0-9]+]], x0
122 ; CHECK: ldxr   [[DEST_REG:x[0-9]+]], [x[[ADDR]]]
124 ; CHECK: stxr   [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x[[ADDR]]]
177 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
178 ; CHECK: ldrb {{w[0-9]+}}, [x[[ADDR]]]
202 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
203 ; CHECK: ldrh {{w[0-9]+}}, [x[[ADDR]]]
227 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
228 ; CHECK: ldr {{w[0-9]+}}, [x[[ADDR]]]
252 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
253 ; CHECK: ldr {{x[0-9]+}}, [x[[ADDR]]]
282 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
283 ; CHECK: strb {{w[0-9]+}}, [x[[ADDR]]]
304 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
305 ; CHECK: strh {{w[0-9]+}}, [x[[ADDR]]]
326 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
327 ; CHECK: str {{w[0-9]+}}, [x[[ADDR]]]
348 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
349 ; CHECK: str {{x[0-9]+}}, [x[[ADDR]]]