Lines Matching refs:XREG
13 ; CHECK: add x[[XREG:[0-9]+]], x0, x1
14 ; CHECK: st1.b { v0 }[1], [x[[XREG]]]
23 ; CHECK: add x[[XREG:[0-9]+]], x0, x1
24 ; CHECK: st1.b { v0 }[0], [x[[XREG]]]
41 ; CHECK: add x[[XREG:[0-9]+]], x0, x1
42 ; CHECK: st1.h { v0 }[1], [x[[XREG]]]
68 ; CHECK: add x[[XREG:[0-9]+]], x0, x1
69 ; CHECK: st1.s { v0 }[1], [x[[XREG]]]
95 ; CHECK: add x[[XREG:[0-9]+]], x0, x1
96 ; CHECK: st1.s { v0 }[1], [x[[XREG]]]
122 ; CHECK: add x[[XREG:[0-9]+]], x0, x1
123 ; CHECK: st1.d { v0 }[1], [x[[XREG]]]
149 ; CHECK: add x[[XREG:[0-9]+]], x0, x1
150 ; CHECK: st1.d { v0 }[1], [x[[XREG]]]
176 ; CHECK: add x[[XREG:[0-9]+]], x0, x1
177 ; CHECK: st1.b { v0 }[1], [x[[XREG]]]
186 ; CHECK: add x[[XREG:[0-9]+]], x0, x1
187 ; CHECK: st1.b { v0 }[0], [x[[XREG]]]
204 ; CHECK: add x[[XREG:[0-9]+]], x0, x1
205 ; CHECK: st1.h { v0 }[1], [x[[XREG]]]
231 ; CHECK: add x[[XREG:[0-9]+]], x0, x1
232 ; CHECK: st1.s { v0 }[1], [x[[XREG]]]
258 ; CHECK: add x[[XREG:[0-9]+]], x0, x1
259 ; CHECK: st1.s { v0 }[1], [x[[XREG]]]