Lines Matching refs:half
4 define <4 x half> @select_64(<4 x half> %a, <4 x half> %b, <4 x i16> %c) #0 {
8 %0 = bitcast <4 x half> %a to <4 x i16>
9 %1 = bitcast <4 x half> %b to <4 x i16>
14 %3 = bitcast <4 x i16> %vbsl5.i to <4 x half>
15 ret <4 x half> %3
19 define <8 x half> @select_128(<8 x half> %a, <8 x half> %b, <8 x i16> %c) #0 {
23 %0 = bitcast <8 x half> %a to <8 x i16>
24 %1 = bitcast <8 x half> %b to <8 x i16>
29 %3 = bitcast <8 x i16> %vbsl5.i to <8 x half>
30 ret <8 x half> %3
36 define <4 x half> @lane_64_64(<4 x half> %a, <4 x half> %b) #0 {
40 %0 = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
41 ret <4 x half> %0
47 define <8 x half> @lane_128_64(<8 x half> %a, <4 x half> %b) #0 {
51 %0 = bitcast <4 x half> %b to <4 x i16>
53 %1 = bitcast <8 x half> %a to <8 x i16>
55 %2 = bitcast <8 x i16> %vset_lane to <8 x half>
56 ret <8 x half> %2
62 define <4 x half> @lane_64_128(<4 x half> %a, <8 x half> %b) #0 {
66 %0 = bitcast <8 x half> %b to <8 x i16>
68 %1 = bitcast <4 x half> %a to <4 x i16>
70 %2 = bitcast <4 x i16> %vset_lane to <4 x half>
71 ret <4 x half> %2
77 define <8 x half> @lane_128_128(<8 x half> %a, <8 x half> %b) #0 {
81 …%0 = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 13, i32 4, i3…
82 ret <8 x half> %0
88 define <4 x half> @ext_64(<4 x half> %a, <4 x half> %b) #0 {
92 %0 = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
93 ret <4 x half> %0
99 define <8 x half> @ext_128(<8 x half> %a, <8 x half> %b) #0 {
103 …%0 = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32…
104 ret <8 x half> %0
110 define <4 x half> @rev32_64(<4 x half> %a) #0 {
114 %0 = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
115 ret <4 x half> %0
121 define <4 x half> @rev64_64(<4 x half> %a) #0 {
125 %0 = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
126 ret <4 x half> %0
132 define <8 x half> @rev32_128(<8 x half> %a) #0 {
136 …%0 = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, …
137 ret <8 x half> %0
143 define <8 x half> @rev64_128(<8 x half> %a) #0 {
147 …%0 = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, …
148 ret <8 x half> %0
152 define <4 x half> @create_64(i64 %a) #0 {
156 %0 = bitcast i64 %a to <4 x half>
157 ret <4 x half> %0
161 define <4 x half> @dup_64(half %a) #0 {
165 %vecinit = insertelement <4 x half> undef, half %a, i32 0
166 %vecinit1 = insertelement <4 x half> %vecinit, half %a, i32 1
167 %vecinit2 = insertelement <4 x half> %vecinit1, half %a, i32 2
168 %vecinit3 = insertelement <4 x half> %vecinit2, half %a, i32 3
169 ret <4 x half> %vecinit3
173 define <8 x half> @dup_128(half %a) #0 {
177 %vecinit = insertelement <8 x half> undef, half %a, i32 0
178 %vecinit1 = insertelement <8 x half> %vecinit, half %a, i32 1
179 %vecinit2 = insertelement <8 x half> %vecinit1, half %a, i32 2
180 %vecinit3 = insertelement <8 x half> %vecinit2, half %a, i32 3
181 %vecinit4 = insertelement <8 x half> %vecinit3, half %a, i32 4
182 %vecinit5 = insertelement <8 x half> %vecinit4, half %a, i32 5
183 %vecinit6 = insertelement <8 x half> %vecinit5, half %a, i32 6
184 %vecinit7 = insertelement <8 x half> %vecinit6, half %a, i32 7
185 ret <8 x half> %vecinit7
189 define <4 x half> @dup_lane_64(<4 x half> %a) #0 {
193 %shuffle = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
194 ret <4 x half> %shuffle
198 define <8 x half> @dup_lane_128(<4 x half> %a) #0 {
202 …%shuffle = shufflevector <4 x half> %a, <4 x half> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i…
203 ret <8 x half> %shuffle
207 define <4 x half> @dup_laneq_64(<8 x half> %a) #0 {
211 %shuffle = shufflevector <8 x half> %a, <8 x half> undef, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
212 ret <4 x half> %shuffle
216 define <8 x half> @dup_laneq_128(<8 x half> %a) #0 {
220 …%shuffle = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i…
221 ret <8 x half> %shuffle
225 define <8 x half> @vcombine(<4 x half> %a, <4 x half> %b) #0 {
229 …%shuffle.i = shufflevector <4 x half> %a, <4 x half> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i3…
230 ret <8 x half> %shuffle.i
234 define <4 x half> @get_high(<8 x half> %a) #0 {
238 %shuffle.i = shufflevector <8 x half> %a, <8 x half> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
239 ret <4 x half> %shuffle.i
244 define <4 x half> @get_low(<8 x half> %a) #0 {
248 %shuffle.i = shufflevector <8 x half> %a, <8 x half> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
249 ret <4 x half> %shuffle.i
253 define <4 x half> @set_lane_64(<4 x half> %a, half %b) #0 {
258 %0 = bitcast half %b to i16
259 %1 = bitcast <4 x half> %a to <4 x i16>
261 %2 = bitcast <4 x i16> %vset_lane to <4 x half>
262 ret <4 x half> %2
267 define <8 x half> @set_lane_128(<8 x half> %a, half %b) #0 {
272 %0 = bitcast half %b to i16
273 %1 = bitcast <8 x half> %a to <8 x i16>
275 %2 = bitcast <8 x i16> %vset_lane to <8 x half>
276 ret <8 x half> %2
280 define half @get_lane_64(<4 x half> %a) #0 {
285 %0 = bitcast <4 x half> %a to <4 x i16>
287 %1 = bitcast i16 %vget_lane to half
288 ret half %1
292 define half @get_lane_128(<8 x half> %a) #0 {
297 %0 = bitcast <8 x half> %a to <8 x i16>
299 %1 = bitcast i16 %vgetq_lane to half
300 ret half %1