Lines Matching refs:SI

1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-pr…
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check…
18 ; SI: s_load_dword [[VAL:s[0-9]+]],
19 ; SI: s_flbit_i32_b32 [[SRESULT:s[0-9]+]], [[VAL]]
20 ; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
21 ; SI: buffer_store_dword [[VRESULT]],
22 ; SI: s_endpgm
32 ; SI: buffer_load_dword [[VAL:v[0-9]+]],
33 ; SI: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]]
34 ; SI: buffer_store_dword [[RESULT]],
35 ; SI: s_endpgm
46 ; SI: buffer_load_dwordx2
47 ; SI: v_ffbh_u32_e32
48 ; SI: v_ffbh_u32_e32
49 ; SI: buffer_store_dwordx2
50 ; SI: s_endpgm
62 ; SI: buffer_load_dwordx4
63 ; SI: v_ffbh_u32_e32
64 ; SI: v_ffbh_u32_e32
65 ; SI: v_ffbh_u32_e32
66 ; SI: v_ffbh_u32_e32
67 ; SI: buffer_store_dwordx4
68 ; SI: s_endpgm
82 ; SI: buffer_load_ubyte [[VAL:v[0-9]+]],
83 ; SI: v_ffbh_u32_e32 [[FFBH:v[0-9]+]], [[VAL]]
84 ; SI: v_add_i32_e32 [[RESULT:v[0-9]+]], vcc, 0xffffffe8, [[FFBH]]
85 ; SI: buffer_store_byte [[RESULT]],
94 ; SI: s_load_dwordx2 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}}
95 ; SI-DAG: v_cmp_eq_i32_e64 vcc, 0, s[[HI]]
96 ; SI-DAG: s_flbit_i32_b32 [[FFBH_LO:s[0-9]+]], s[[LO]]
97 ; SI-DAG: s_add_i32 [[ADD:s[0-9]+]], [[FFBH_LO]], 32
98 ; SI-DAG: s_flbit_i32_b32 [[FFBH_HI:s[0-9]+]], s[[HI]]
99 ; SI-DAG: v_mov_b32_e32 [[VFFBH_LO:v[0-9]+]], [[FFBH_LO]]
100 ; SI-DAG: v_mov_b32_e32 [[VFFBH_HI:v[0-9]+]], [[FFBH_HI]]
101 ; SI-DAG: v_cndmask_b32_e32 v[[CTLZ:[0-9]+]], [[VFFBH_HI]], [[VFFBH_LO]]
102 ; SI-DAG: v_mov_b32_e32 v[[CTLZ_HI:[0-9]+]], 0{{$}}
103 ; SI: {{buffer|flat}}_store_dwordx2 v{{\[}}[[CTLZ]]:[[CTLZ_HI]]{{\]}}
119 ; SI-DAG: {{buffer|flat}}_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
120 ; SI-DAG: v_cmp_eq_i32_e64 [[CMPHI:s\[[0-9]+:[0-9]+\]]], 0, v[[HI]]
121 ; SI-DAG: v_ffbh_u32_e32 [[FFBH_LO:v[0-9]+]], v[[LO]]
122 ; SI-DAG: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, 32, [[FFBH_LO]]
123 ; SI-DAG: v_ffbh_u32_e32 [[FFBH_HI:v[0-9]+]], v[[HI]]
124 ; SI-DAG: v_cndmask_b32_e64 v[[CTLZ:[0-9]+]], [[FFBH_HI]], [[FFBH_LO]]
125 ; SI-DAG: v_mov_b32_e32 v[[CTLZ_HI:[0-9]+]], 0{{$}}
126 ; SI: {{buffer|flat}}_store_dwordx2 {{.*}}v{{\[}}[[CTLZ]]:[[CTLZ_HI]]{{\]}}
150 ; SI: buffer_load_dword [[VAL:v[0-9]+]],
151 ; SI: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]]
152 ; SI: buffer_store_dword [[RESULT]],
163 ; SI: buffer_load_dword [[VAL:v[0-9]+]],
164 ; SI: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]]
165 ; SI: buffer_store_dword [[RESULT]],
176 ; SI: buffer_load_ubyte [[VAL:v[0-9]+]],
177 ; SI: v_ffbh_u32_e32 [[FFBH:v[0-9]+]], [[VAL]]
178 ; SI: buffer_store_byte [[FFBH]],
189 ; SI: buffer_load_dword [[VAL:v[0-9]+]],
190 ; SI-DAG: v_ffbh_u32_e32 [[RESULT0:v[0-9]+]], [[VAL]]
191 ; SI-DAG: v_cmp_eq_i32_e32 vcc, 0, [[VAL]]
192 ; SI-DAG: v_cndmask_b32_e64 [[RESULT1:v[0-9]+]], 0, 1, vcc
193 ; SI-DAG: buffer_store_dword [[RESULT0]]
194 ; SI-DAG: buffer_store_byte [[RESULT1]]
195 ; SI: s_endpgm
208 ; SI: buffer_load_dword
209 ; SI: v_ffbh_u32_e32
210 ; SI: v_cmp
211 ; SI: v_cndmask
212 ; SI: buffer_store_dword
224 ; SI: buffer_load_dword
225 ; SI: v_ffbh_u32_e32
226 ; SI: v_cmp
227 ; SI: v_cndmask
228 ; SI: buffer_store_dword
240 ; SI: buffer_load_dword
241 ; SI: v_ffbh_u32_e32
242 ; SI: v_cmp
243 ; SI: v_cndmask
244 ; SI: buffer_store_dword
256 ; SI: buffer_load_dword
257 ; SI: v_ffbh_u32_e32
258 ; SI: v_cmp
259 ; SI: v_cndmask
260 ; SI: buffer_store_dword