Lines Matching refs:vminnm
25 ; CHECK: vminnm.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
28 %tmp3 = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
34 ; CHECK: vminnm.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
37 %tmp3 = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
45 ; CHECK-NOT: vminnm.f32
53 ; CHECK-NOT: vminnm.f64
61 ; CHECK-NOT: vminnm.f32
69 ; CHECK-NOT: vminnm.f64
77 ; CHECK-NOT: vminnm.f32
85 ; CHECK-NOT: vminnm.f32
93 ; CHECK-NOT: vminnm.f32
101 ; CHECK-NOT: vminnm.f64
175 ; CHECK: vminnm.f32
176 ; CHECK-NOT: vminnm.f32
186 ; CHECK: vminnm.f64
187 ; CHECK-NOT: vminnm.f64
197 ; CHECK: vminnm.f32
198 ; CHECK-NOT: vminnm.f32
208 ; CHECK: vminnm.f64
209 ; CHECK-NOT: vminnm.f64
219 ; CHECK: vminnm.f32
220 ; CHECK-NOT: vminnm.f32
230 ; CHECK: vminnm.f32
231 ; CHECK-NOT: vminnm.f32
241 ; CHECK: vminnm.f32
242 ; CHECK-NOT: vminnm.f32
252 ; CHECK: vminnm.f64
253 ; CHECK-NOT: vminnm.f64
351 ; CHECK-NOT: vminnm.f32
362 ; CHECK: vminnm.f32
373 ; CHECK-NOT: vminnm.f32
384 ; CHECK: vminnm.f32
393 declare <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
394 declare <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float>, <2 x float>) nounwind readnone