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Lines Matching refs:bankWidth

710     if (tileSize * pTileInfo->bankWidth * pTileInfo->bankHeight > m_rowSize)  in HwlReduceBankWidthHeight()
715 if (stillGreater && pTileInfo->bankWidth > 1) in HwlReduceBankWidthHeight()
717 while (stillGreater && pTileInfo->bankWidth > 0) in HwlReduceBankWidthHeight()
719 pTileInfo->bankWidth >>= 1; in HwlReduceBankWidthHeight()
721 if (pTileInfo->bankWidth == 0) in HwlReduceBankWidthHeight()
723 pTileInfo->bankWidth = 1; in HwlReduceBankWidthHeight()
728 tileSize * pTileInfo->bankWidth * pTileInfo->bankHeight > m_rowSize; in HwlReduceBankWidthHeight()
734 (tileSize * pTileInfo->bankWidth) in HwlReduceBankWidthHeight()
744 (tileSize * pipes * pTileInfo->bankWidth) in HwlReduceBankWidthHeight()
771 tileSize * pTileInfo->bankWidth * pTileInfo->bankHeight > m_rowSize; in HwlReduceBankWidthHeight()
782 tileSize, pTileInfo->bankWidth, pTileInfo->bankHeight, m_rowSize)); in HwlReduceBankWidthHeight()
839 (tileSize * pTileInfo->bankWidth) in ComputeSurfaceAlignmentsMacroTiled()
851 (tileSize * pipes * pTileInfo->bankWidth) in ComputeSurfaceAlignmentsMacroTiled()
867 macroTileWidth = MicroTileWidth * pTileInfo->bankWidth * pipes * in ComputeSurfaceAlignmentsMacroTiled()
886 pTileInfo->bankWidth * pTileInfo->banks * pTileInfo->bankHeight * tileSize; in ComputeSurfaceAlignmentsMacroTiled()
941 switch (pTileInfo->bankWidth) in SanityCheckMacroTiled()
1063 bytesPerTile * HwlGetPipes(pTileInfo) * pTileInfo->bankWidth * pTileInfo->macroAspectRatio; in ComputeSurfaceMipLevelTileMode()
1066 bytesPerTile * pTileInfo->bankWidth * pTileInfo->bankHeight; in ComputeSurfaceMipLevelTileMode()
1572 (MicroTileWidth * pTileInfo->bankWidth * numPipes) * pTileInfo->macroAspectRatio; in ComputeSurfaceAddrFromCoordMacroTiled()
1615 tileColumnIndex = ((x / MicroTileWidth) / numPipes) % pTileInfo->bankWidth; in ComputeSurfaceAddrFromCoordMacroTiled()
1616 tileIndex = (tileRowIndex * pTileInfo->bankWidth) + tileColumnIndex; in ComputeSurfaceAddrFromCoordMacroTiled()
2229 UINT_32 macroWidth = pTileInfo->bankWidth * pipes * pTileInfo->macroAspectRatio; in ComputeSurfaceCoordFromAddrMacroTiled()
2278 my = (tileIndex / pTileInfo->bankWidth) % pTileInfo->bankHeight * MicroTileHeight; in ComputeSurfaceCoordFromAddrMacroTiled()
2279 mx = (tileIndex % pTileInfo->bankWidth) * pipes * MicroTileWidth; in ComputeSurfaceCoordFromAddrMacroTiled()
2342 UINT_32 xBit = x / (MicroTileWidth * pTileInfo->bankWidth * numPipes); in ComputeSurfaceCoord2DFromBankPipe()
2808 UINT_32 bankWidth = pTileInfo->bankWidth; in ComputeBankFromCoord() local
2811 UINT_32 tx = x / MicroTileWidth / (bankWidth * pipes); in ComputeBankFromCoord()
3950 (pTileInfo->bankWidth != 0) || in IsTileInfoAllZero()
3982 pLeft->bankWidth == pRight->bankWidth && in HwlTileInfoEqual()
4037 switch (pTileInfoIn->bankWidth) in HwlConvertTileInfoToHW()
4040 pTileInfoOut->bankWidth = 0; in HwlConvertTileInfoToHW()
4043 pTileInfoOut->bankWidth = 1; in HwlConvertTileInfoToHW()
4046 pTileInfoOut->bankWidth = 2; in HwlConvertTileInfoToHW()
4049 pTileInfoOut->bankWidth = 3; in HwlConvertTileInfoToHW()
4054 pTileInfoOut->bankWidth = 0; in HwlConvertTileInfoToHW()
4153 switch (pTileInfoIn->bankWidth) in HwlConvertTileInfoToHW()
4156 pTileInfoOut->bankWidth = 1; in HwlConvertTileInfoToHW()
4159 pTileInfoOut->bankWidth = 2; in HwlConvertTileInfoToHW()
4162 pTileInfoOut->bankWidth = 4; in HwlConvertTileInfoToHW()
4165 pTileInfoOut->bankWidth = 8; in HwlConvertTileInfoToHW()
4170 pTileInfoOut->bankWidth = 1; in HwlConvertTileInfoToHW()
4327 ADDR_ASSERT(tileInfo.bankWidth == pIn->pTileInfo->bankWidth); in HwlComputeSurfaceInfo()