Lines Matching refs:ADDR_TILEINFO
49 ADDR_TILEINFO info;
102 ADDR_TILEINFO* pTileInfo, UINT_32* pBitPosition) const;
107 ADDR_TILEINFO* pTileInfo, UINT_32* pX, UINT_32* pY, UINT_32* pSlice) const;
124 ADDR_TILEINFO* pInfo, AddrTileMode* pMode = 0, AddrTileType* pType = 0) const;
128 UINT_32 bpp, ADDR_TILEINFO* pTileInfo) const;
137 ADDR_TILEINFO* pTileInfo) const;
139 virtual UINT_32 HwlGetPipes(const ADDR_TILEINFO* pTileInfo) const;
156 ADDR_TILEINFO* inputTileInfo, ADDR_TILEINFO* outputTileInfo,
171 const ADDR_TILEINFO* pLeft, const ADDR_TILEINFO* pRight) const;
182 ADDR_TILEINFO* pTileInfo) const in HwlSanityCheckMacroTiled()
199 ADDR_TILEINFO* pTileInfo) const;
202 UINT_32 tileX, UINT_32 bank, ADDR_TILEINFO* pTileInfo) const;
205 const ADDR_TILEINFO* pInfo, AddrTileMode mode, AddrTileType type,
225 ADDR_TILEINFO* pTileInfo) const in HwlReduceBankWidthHeight()