121 void si_pm4_free_state(struct si_context *sctx,  in si_pm4_free_state()  argument
128 	if (idx != ~0 && sctx->emitted.array[idx] == state) {  in si_pm4_free_state()
129 		sctx->emitted.array[idx] = NULL;  in si_pm4_free_state()
135 void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state)  in si_pm4_emit()  argument
137 	struct radeon_winsys_cs *cs = sctx->b.gfx.cs;  in si_pm4_emit()
140 		radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, state->bo[i],  in si_pm4_emit()
149 		radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, ib,  in si_pm4_emit()
160 void si_pm4_emit_dirty(struct si_context *sctx)  in si_pm4_emit_dirty()  argument
163 		struct si_pm4_state *state = sctx->queued.array[i];  in si_pm4_emit_dirty()
165 		if (!state || sctx->emitted.array[i] == state)  in si_pm4_emit_dirty()
168 		si_pm4_emit(sctx, state);  in si_pm4_emit_dirty()
169 		sctx->emitted.array[i] = state;  in si_pm4_emit_dirty()
173 void si_pm4_reset_emitted(struct si_context *sctx)  in si_pm4_reset_emitted()  argument
175 	memset(&sctx->emitted, 0, sizeof(sctx->emitted));  in si_pm4_reset_emitted()
178 void si_pm4_upload_indirect_buffer(struct si_context *sctx,  in si_pm4_upload_indirect_buffer()  argument
181 	struct pipe_screen *screen = sctx->b.b.screen;  in si_pm4_upload_indirect_buffer()
185 	if (sctx->b.chip_class < CIK)  in si_pm4_upload_indirect_buffer()
199 	if (sctx->screen->b.info.gfx_ib_pad_with_type2) {  in si_pm4_upload_indirect_buffer()
207 	pipe_buffer_write(&sctx->b.b, &state->indirect_buffer->b.b,  in si_pm4_upload_indirect_buffer()