Lines Matching refs:VirtRegMap
153 VirtRegMap &vrm, unsigned reg) { in conflictsWithPhysReg()
1062 MRInfo |= (unsigned)VirtRegMap::isMod; in FilterFoldedOps()
1066 MRInfo = VirtRegMap::isModRef; in FilterFoldedOps()
1069 MRInfo |= (unsigned)VirtRegMap::isRef; in FilterFoldedOps()
1082 VirtRegMap &vrm, MachineInstr *DefMI, in tryFoldMemoryOperand()
1104 if (DefMI && (MRInfo & VirtRegMap::isMod)) in tryFoldMemoryOperand()
1116 vrm.virtFolded(Reg, MI, fmi, (VirtRegMap::ModRef)MRInfo); in tryFoldMemoryOperand()
1142 if (ReMat && (MRInfo & VirtRegMap::isMod)) in canFoldMemoryOperand()
1171 VirtRegMap &vrm) { in rewriteImplicitOps()
1200 VirtRegMap &vrm, in rewriteInstructionForSpills()
1323 if (ReMatIds[VNI->id] == VirtRegMap::MAX_STACK_SLOT) { in rewriteInstructionForSpills()
1339 vrm.getStackSlot(NewVReg) == VirtRegMap::NO_STACK_SLOT) { in rewriteInstructionForSpills()
1342 assert(Slot != VirtRegMap::NO_STACK_SLOT); in rewriteInstructionForSpills()
1423 VirtRegMap &vrm, in rewriteInstructionsForSpills()
1448 if (Slot != VirtRegMap::MAX_STACK_SLOT || isLoadSS) { in rewriteInstructionsForSpills()
1676 LiveIntervals::handleSpilledImpDefs(const LiveInterval &li, VirtRegMap &vrm, in handleSpilledImpDefs()
1742 const MachineLoopInfo *loopInfo, VirtRegMap &vrm) { in addIntervalsForSpills()
1766 ReMatIds.resize(NumValNums, VirtRegMap::MAX_STACK_SLOT); in addIntervalsForSpills()
1768 unsigned Slot = VirtRegMap::MAX_STACK_SLOT; in addIntervalsForSpills()
1786 assert(Slot != VirtRegMap::MAX_STACK_SLOT); in addIntervalsForSpills()
1862 if (vrm.getStackSlot(li.reg) == VirtRegMap::NO_STACK_SLOT) in addIntervalsForSpills()
2101 unsigned PhysReg, VirtRegMap &vrm) { in spillPhysRegAroundRegDefsUses()