127 …ITE(data, ioaddr) outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_S…
281 	outl(DM910X_RESET, ioaddr + DCR0);	/* RESET MAC */  in dmfe_init_dm910x()
283 	outl(db->cr0_data, ioaddr + DCR0);  in dmfe_init_dm910x()
294 	outl(0x180, ioaddr + DCR12);	/* Let bit 7 output port */  in dmfe_init_dm910x()
296 		outl(0x80, ioaddr + DCR12);	/* Issue RESET signal */  in dmfe_init_dm910x()
299 	outl(0x0, ioaddr + DCR12);	/* Clear RESET signal */  in dmfe_init_dm910x()
313 	outl(virt_to_le32desc(&txd[0]), ioaddr + DCR4);	/* TX DESC address */  in dmfe_init_dm910x()
316 	outl(virt_to_le32desc(&rxd[0]), ioaddr + DCR3);	/* RX DESC address */  in dmfe_init_dm910x()
330 	outl(db->cr7_data, ioaddr + DCR7);  in dmfe_init_dm910x()
332 	outl(db->cr15_data, ioaddr + DCR15);  in dmfe_init_dm910x()
410 	outl(0, BASE + DCR7);  in dmfe_transmit()
426 	outl(0x1, BASE + DCR1);  in dmfe_transmit()
427 	outl(db->cr7_data, BASE + DCR7);  in dmfe_transmit()
439 	outl(DM910X_RESET, BASE + DCR0);  in dmfe_disable()
520 	outl(virt_to_le32desc(&txd[0]), ioaddr + DCR4);	/* TX DESC address */  in dmfe_descriptor_init()
523 	outl(virt_to_le32desc(&rxd[0]), ioaddr + DCR3);	/* RX DESC address */  in dmfe_descriptor_init()
564 	outl(cr6_tmp, ioaddr + DCR6);  in update_cr6()
566 	outl(cr6_data, ioaddr + DCR6);  in update_cr6()
652 	outl(0x1, BASE + DCR1);	/* Issue Tx polling */  in send_filter_frame()
667 	outl(CR9_SROM_READ, cr9_ioaddr);  in read_srom_word()
668 	outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);  in read_srom_word()
682 	outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);  in read_srom_word()
685 		outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);  in read_srom_word()
690 		outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);  in read_srom_word()
694 	outl(CR9_SROM_READ, cr9_ioaddr);  in read_srom_word()
992 	outl(phy_data, ioaddr);	/* MII Clock Low */  in phy_write_1bit()
994 	outl(phy_data | MDCLKH, ioaddr);	/* MII Clock High */  in phy_write_1bit()
996 	outl(phy_data, ioaddr);	/* MII Clock Low */  in phy_write_1bit()
1009 	outl(0x50000, ioaddr);  in phy_read_1bit()
1012 	outl(0x40000, ioaddr);  in phy_read_1bit()