267 #define eepro_full_reset(ioaddr)	outb(RESET_CMD, ioaddr); udelay(255);
272     outb ( SEL_RESET_CMD, ioaddr ); \
278 #define	eepro_clear_int(ioaddr)	outb(ALL_MASK, ioaddr + STATUS_REG)
281 #define	eepro_en_rx(ioaddr)	outb(RCV_ENABLE_CMD, ioaddr)
284 #define	eepro_dis_rx(ioaddr)	outb(RCV_DISABLE_CMD, ioaddr)
287 #define eepro_sw2bank0(ioaddr) outb(BANK0_SELECT, ioaddr)
288 #define eepro_sw2bank1(ioaddr) outb(BANK1_SELECT, ioaddr)
289 #define eepro_sw2bank2(ioaddr) outb(BANK2_SELECT, ioaddr)
309 		outb(temp_reg & 0xEF, nic->ioaddr + eeprom_reg);  in eepro_reset()
311 		outb(nic->node_addr[i], nic->ioaddr + I_ADD_REG0 + i);  in eepro_reset()
314 	outb(temp_reg | XMT_Chain_Int | XMT_Chain_ErrStop  in eepro_reset()
317 	outb(temp_reg | 0x14, nic->ioaddr + REG2);  in eepro_reset()
319 	outb(temp_reg & 0x3F, nic->ioaddr + REG3);	/* clear test mode */  in eepro_reset()
323 	outb(RCV_LOWER_LIMIT, nic->ioaddr + RCV_LOWER_LIMIT_REG);  in eepro_reset()
324 	outb(RCV_UPPER_LIMIT, nic->ioaddr + RCV_UPPER_LIMIT_REG);  in eepro_reset()
325 	outb(XMT_LOWER_LIMIT, nic->ioaddr + xmt_lower_limit_reg);  in eepro_reset()
326 	outb(XMT_UPPER_LIMIT, nic->ioaddr + xmt_upper_limit_reg);  in eepro_reset()
357 	outb(0x40, nic->ioaddr + STATUS_REG);  in eepro_poll()
444 	outb(XMT_CMD, nic->ioaddr);  in eepro_transmit()
469 	outb(STOP_RCV_CMD, nic->ioaddr);  in eepro_disable()
501 		outb(0x00, ioaddr + STATUS_REG);  in read_eeprom()
504 	outb(ctrl_val, ee_addr);  in read_eeprom()
508 		outb(outval, ee_addr);  in read_eeprom()
509 		outb(outval | EESK, ee_addr);	/* EEPROM clock tick */  in read_eeprom()
511 		outb(outval, ee_addr);		/* finish EEPROM clock tick */  in read_eeprom()
514 	outb(ctrl_val, ee_addr);  in read_eeprom()
516 		outb(ctrl_val | EESK, ee_addr);  in read_eeprom()
519 		outb(ctrl_val, ee_addr);  in read_eeprom()
524 	outb(ctrl_val | EESK, ee_addr);  in read_eeprom()
526 	outb(ctrl_val, ee_addr);  in read_eeprom()