Lines Matching refs:Emit
83 selector->Emit(opcode, g.DefineAsRegister(node), in VisitRR()
89 selector->Emit(opcode, g.DefineAsRegister(node), in VisitRRR()
98 selector->Emit( in VisitRRRR()
106 selector->Emit(opcode, g.DefineAsRegister(node), in VisitRRI()
113 selector->Emit(opcode, g.DefineAsRegister(node), in VisitRRIR()
294 selector->Emit(opcode, output_count, outputs, input_count, inputs); in VisitBinop()
296 selector->Emit(opcode, output_count, outputs, input_count, inputs); in VisitBinop()
314 selector->Emit(div_opcode, result_operand, left_operand, right_operand); in EmitDiv()
320 selector->Emit(f64i32_opcode, left_double_operand, left_operand); in EmitDiv()
321 selector->Emit(f64i32_opcode, right_double_operand, right_operand); in EmitDiv()
322 selector->Emit(kArmVdivF64, result_double_operand, left_double_operand, in EmitDiv()
324 selector->Emit(i32f64_opcode, result_operand, result_double_operand); in EmitDiv()
349 selector->Emit(kArmMls, result_operand, div_operand, right_operand, in VisitMod()
353 selector->Emit(kArmMul, mul_operand, div_operand, right_operand); in VisitMod()
354 selector->Emit(kArmSub | AddressingModeField::encode(kMode_Operand2_R), in VisitMod()
377 selector->Emit(opcode, 1, output, input_count, inputs); in EmitLoad()
396 selector->Emit(opcode, 0, nullptr, input_count, inputs); in EmitStore()
494 Emit(code, 0, nullptr, input_count, inputs, temp_count, temps); in VisitStore()
555 Emit(kArmVmovF32U32, g.DefineAsRegister(node), temp); in VisitUnalignedLoad()
581 Emit(add_opcode, 1, &addr, input_count, inputs); in VisitUnalignedLoad()
587 Emit(opcode, fp_lo, addr, g.TempImmediate(0)); in VisitUnalignedLoad()
588 Emit(opcode, fp_hi, addr, g.TempImmediate(4)); in VisitUnalignedLoad()
589 Emit(kArmVmovF64U32U32, g.DefineAsRegister(node), fp_lo, fp_hi); in VisitUnalignedLoad()
617 Emit(kArmVmovU32F32, inputs[0], g.UseRegister(value)); in VisitUnalignedStore()
632 Emit(kArmVmovU32U32F64, arraysize(fp), fp, input_count, in VisitUnalignedStore()
642 Emit(kArmAdd | AddressingModeField::encode(kMode_Operand2_I), base4, in VisitUnalignedStore()
696 Emit(opcode | AddressingModeField::encode(kMode_Offset_RR), in VisitCheckedLoad()
743 Emit(opcode | AddressingModeField::encode(kMode_Offset_RR), g.NoOutput(), in VisitCheckedStore()
758 selector->Emit(opcode, g.DefineAsRegister(node), g.UseRegister(left), in EmitBic()
762 selector->Emit(opcode | AddressingModeField::encode(kMode_Operand2_R), in EmitBic()
773 selector->Emit(kArmUbfx, g.DefineAsRegister(node), g.UseRegister(left), in EmitUbfx()
812 Emit((value == 0xff) ? kArmUxtb : kArmUxth, in VisitWord32And()
834 Emit(kArmUxth, g.DefineAsRegister(m.node()), in VisitWord32And()
840 Emit(kArmBic | AddressingModeField::encode(kMode_Operand2_I), in VisitWord32And()
861 Emit(kArmBfc, g.DefineSameAsFirst(node), g.UseRegister(m.left().node()), in VisitWord32And()
885 Emit(opcode, g.DefineAsRegister(node), value_operand, shift_operand); in VisitWord32Xor()
888 Emit(opcode | AddressingModeField::encode(kMode_Operand2_R), in VisitWord32Xor()
932 selector->Emit(opcode, output_count, outputs, input_count, inputs); in VisitShift()
934 selector->Emit(opcode, output_count, outputs, input_count, inputs); in VisitShift()
984 Emit(kArmSxth, g.DefineAsRegister(node), in VisitWord32Sar()
988 Emit(kArmSxtb, g.DefineAsRegister(node), in VisitWord32Sar()
992 Emit(kArmSbfx, g.DefineAsRegister(node), in VisitWord32Sar()
1017 Emit(kArmAddPair, 2, outputs, 4, inputs); in VisitInt32PairAdd()
1021 Emit(kArmAdd | AddressingModeField::encode(kMode_Operand2_R), in VisitInt32PairAdd()
1042 Emit(kArmSubPair, 2, outputs, 4, inputs); in VisitInt32PairSub()
1046 Emit(kArmSub | AddressingModeField::encode(kMode_Operand2_R), in VisitInt32PairSub()
1065 Emit(kArmMulPair, 2, outputs, 4, inputs); in VisitInt32PairMul()
1069 Emit(kArmMul | AddressingModeField::encode(kMode_Operand2_R), in VisitInt32PairMul()
1108 selector->Emit(opcode, output_count, outputs, 3, inputs, temp_count, temps); in VisitWord32PairShift()
1148 Emit(kArmMla, g.DefineAsRegister(node), in VisitInt32Add()
1156 Emit(kArmSmmla, g.DefineAsRegister(node), in VisitInt32Add()
1165 Emit(kArmUxtab, g.DefineAsRegister(node), in VisitInt32Add()
1170 Emit(kArmUxtah, g.DefineAsRegister(node), in VisitInt32Add()
1182 Emit(kArmSxtab, g.DefineAsRegister(node), in VisitInt32Add()
1187 Emit(kArmSxtah, g.DefineAsRegister(node), in VisitInt32Add()
1202 Emit(kArmMla, g.DefineAsRegister(node), in VisitInt32Add()
1210 Emit(kArmSmmla, g.DefineAsRegister(node), in VisitInt32Add()
1219 Emit(kArmUxtab, g.DefineAsRegister(node), in VisitInt32Add()
1224 Emit(kArmUxtah, g.DefineAsRegister(node), in VisitInt32Add()
1236 Emit(kArmSxtab, g.DefineAsRegister(node), in VisitInt32Add()
1241 Emit(kArmSxtah, g.DefineAsRegister(node), in VisitInt32Add()
1262 Emit(kArmMls, g.DefineAsRegister(node), g.UseRegister(mright.left().node()), in VisitInt32Sub()
1280 selector->Emit(kArmSmull, 2, outputs, 2, inputs); in EmitInt32MulWithOverflow()
1287 selector->Emit(opcode, g.NoOutput(), temp_operand, result_operand, shift_31, in EmitInt32MulWithOverflow()
1294 selector->Emit(opcode, g.DefineAsRegister(cont->result()), temp_operand, in EmitInt32MulWithOverflow()
1300 selector->Emit(opcode, 0, nullptr, 4, in); in EmitInt32MulWithOverflow()
1312 Emit(kArmAdd | AddressingModeField::encode(kMode_Operand2_R_LSL_I), in VisitInt32Mul()
1319 Emit(kArmRsb | AddressingModeField::encode(kMode_Operand2_R_LSL_I), in VisitInt32Mul()
1334 Emit(kArmUmull, arraysize(outputs), outputs, arraysize(inputs), inputs); in VisitUint32MulHigh()
1433 Emit(kArmVmlaF32, g.DefineSameAsFirst(node),
1440 Emit(kArmVmlaF32, g.DefineSameAsFirst(node), g.UseRegister(m.left().node()),
1454 Emit(kArmVmlaF64, g.DefineSameAsFirst(node), in VisitFloat64Add()
1461 Emit(kArmVmlaF64, g.DefineSameAsFirst(node), g.UseRegister(m.left().node()), in VisitFloat64Add()
1474 Emit(kArmVmlsF32, g.DefineSameAsFirst(node), g.UseRegister(m.left().node()), in VisitFloat32Sub()
1487 Emit(kArmVmlsF64, g.DefineSameAsFirst(node), g.UseRegister(m.left().node()), in VisitFloat64Sub()
1497 Emit(kArmVmodF64, g.DefineAsFixed(node, d0), g.UseFixed(node->InputAt(0), d0), in VisitFloat64Mod()
1504 Emit(opcode, g.DefineAsFixed(node, d0), g.UseFixed(node->InputAt(0), d0), in VisitFloat64Ieee754Binop()
1512 Emit(opcode, g.DefineAsFixed(node, d0), g.UseFixed(node->InputAt(0), d0)) in VisitFloat64Ieee754Unop()
1523 Emit(kArchPrepareCallCFunction | in EmitPrepareArguments()
1532 Emit(kArmPoke | MiscField::encode(slot), g.NoOutput(), in EmitPrepareArguments()
1541 Emit(kArmPush, g.NoOutput(), g.UseRegister(input.node())); in EmitPrepareArguments()
1560 selector->Emit(opcode, g.NoOutput(), left, right, in VisitCompare()
1566 selector->Emit(opcode, g.DefineAsRegister(cont->result()), left, right); in VisitCompare()
1569 selector->Emit(opcode, g.NoOutput(), left, right, in VisitCompare()
1763 selector->Emit(opcode, output_count, outputs, input_count, inputs); in VisitWordCompare()
1765 selector->Emit(opcode, output_count, outputs, input_count, inputs); in VisitWordCompare()
1915 selector->Emit(opcode, g.NoOutput(), value_operand, value_operand, in VisitWordCompareZero()
1921 selector->Emit(opcode, g.DefineAsRegister(cont->result()), value_operand, in VisitWordCompareZero()
1925 selector->Emit(opcode, g.NoOutput(), value_operand, value_operand, in VisitWordCompareZero()
1981 Emit(kArmSub | AddressingModeField::encode(kMode_Operand2_I), in VisitSwitch()
2104 Emit(kArmVmovF64U32U32, g.DefineAsRegister(node), g.UseRegister(right), in VisitFloat64InsertLowWord32()
2108 Emit(kArmVmovLowF64U32, g.DefineSameAsFirst(node), g.UseRegister(left), in VisitFloat64InsertLowWord32()
2120 Emit(kArmVmovF64U32U32, g.DefineAsRegister(node), g.UseRegister(left), in VisitFloat64InsertHighWord32()
2124 Emit(kArmVmovHighF64U32, g.DefineSameAsFirst(node), g.UseRegister(left), in VisitFloat64InsertHighWord32()
2148 Emit(opcode | AddressingModeField::encode(kMode_Offset_RR), in VisitAtomicLoad()
2181 Emit(code, 0, nullptr, input_count, inputs); in VisitAtomicStore()