Lines Matching refs:vassert
180 do { vassert(__curr_is_Thumb); } while (0)
183 do { vassert(! __curr_is_Thumb); } while (0)
214 vassert(sh >= 0 && sh < 32); in ROR32()
297 vassert(i < 256); in mkU8()
372 vassert(0); in loadGuardedLE()
374 vassert(loaded != NULL); in loadGuardedLE()
388 vassert(isPlausibleIRType(ty)); in newTemp()
402 vassert(rot >= 0 && rot < 32); in genROR32()
524 default: vassert(0); in integerGuestRegOffset()
531 vassert(iregNo < 16); in llGetIReg()
541 vassert(iregNo < 16); in getIRegA()
549 vassert(0 == (guest_R15_curr_instr_notENC & 3)); in getIRegA()
563 vassert(iregNo < 16); in getIRegT()
566 vassert(0 == (guest_R15_curr_instr_notENC & 1)); in getIRegT()
578 vassert(iregNo < 16); in llPutIReg()
579 vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32); in llPutIReg()
614 vassert(r15written == False); in putIRegA()
615 vassert(r15guard == IRTemp_INVALID); in putIRegA()
616 vassert(r15kind == Ijk_Boring); in putIRegA()
634 vassert(iregNo >= 0 && iregNo <= 14); in putIRegT()
651 vassert(r <= 15); in isBadRegT()
697 default: vassert(0); in doubleGuestRegOffset()
704 vassert(dregNo < 32); in llGetDReg()
716 vassert(dregNo < 32); in llPutDReg()
717 vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_F64); in llPutDReg()
747 vassert(dregNo < 32); in llGetDRegI64()
759 vassert(dregNo < 32); in llPutDRegI64()
760 vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I64); in llPutDRegI64()
806 default: vassert(0); in quadGuestRegOffset()
813 vassert(qregNo < 16); in llGetQReg()
825 vassert(qregNo < 16); in llPutQReg()
826 vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_V128); in llPutQReg()
861 vassert(fregNo < 64); in floatGuestRegOffset()
867 vassert(0); in floatGuestRegOffset()
875 vassert(fregNo < 32); in llGetFReg()
881 vassert(fregNo < 64); in llGetFReg_up_to_64()
893 vassert(fregNo < 32); in llPutFReg()
894 vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_F32); in llPutFReg()
900 vassert(fregNo < 64); in llPutFReg_up_to_64()
901 vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_F32); in llPutFReg_up_to_64()
938 default: vassert(0); /* awaiting more cases */ in putMiscReg32()
940 vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32); in putMiscReg32()
1007 vassert( flagNo >= 0 && flagNo <= 3 ); in put_GEFLAG32()
1008 vassert( lowbits_to_ignore == 0 || in put_GEFLAG32()
1020 default: vassert(0); in put_GEFLAG32()
1033 default: vassert(0); in get_GEFLAG32()
1155 vassert(typeOfIRExpr(irsb->tyenv, cond) == Ity_I32); in mk_armg_calculate_condition_dyn()
1199 vassert(cond >= 0 && cond <= 15); in mk_armg_calculate_condition()
1340 vassert(typeOfIRTemp(irsb->tyenv, t_dep1 == Ity_I32)); in setFlags_D1_D2_ND()
1341 vassert(typeOfIRTemp(irsb->tyenv, t_dep2 == Ity_I32)); in setFlags_D1_D2_ND()
1342 vassert(typeOfIRTemp(irsb->tyenv, t_ndep == Ity_I32)); in setFlags_D1_D2_ND()
1343 vassert(cc_op >= ARMG_CC_OP_COPY && cc_op < ARMG_CC_OP_NUMBER); in setFlags_D1_D2_ND()
1426 vassert(guardT != IRTemp_INVALID); in mk_skip_over_A32_if_cond_is_false()
1427 vassert(0 == (guest_R15_curr_instr_notENC & 3)); in mk_skip_over_A32_if_cond_is_false()
1443 vassert(guardT != IRTemp_INVALID); in mk_skip_over_T16_if_cond_is_false()
1444 vassert(0 == (guest_R15_curr_instr_notENC & 1)); in mk_skip_over_T16_if_cond_is_false()
1461 vassert(guardT != IRTemp_INVALID); in mk_skip_over_T32_if_cond_is_false()
1462 vassert(0 == (guest_R15_curr_instr_notENC & 1)); in mk_skip_over_T32_if_cond_is_false()
1478 vassert(t != IRTemp_INVALID); in gen_SIGILL_T_if_nonzero()
1479 vassert(0 == (guest_R15_curr_instr_notENC & 1)); in gen_SIGILL_T_if_nonzero()
1575 vassert(write_nzcvq || write_ge); in desynthesise_APSR()
1771 vassert(shift_amt >= 1 && shift_amt <= 31); in compute_result_and_C_after_LSL_by_imm5()
1883 vassert(shift_amt >= 1 && shift_amt <= 31); in compute_result_and_C_after_LSR_by_imm5()
1993 vassert(shift_amt >= 1 && shift_amt <= 31); in compute_result_and_C_after_ASR_by_imm5()
2170 vassert(shift_amt < 32); in compute_result_and_C_after_shift_by_imm5()
2171 vassert(how < 4); in compute_result_and_C_after_shift_by_imm5()
2214 vassert(shift_amt >= 1 && shift_amt <= 31); in compute_result_and_C_after_shift_by_imm5()
2233 vassert(0); in compute_result_and_C_after_shift_by_imm5()
2264 vassert(how < 4); in compute_result_and_C_after_shift_by_reg()
2292 vassert(0); in compute_result_and_C_after_shift_by_reg()
2317 vassert(insn_25 <= 0x1); in mk_shifter_operand()
2318 vassert(insn_11_0 <= 0xFFF); in mk_shifter_operand()
2320 vassert(shop && *shop == IRTemp_INVALID); in mk_shifter_operand()
2324 vassert(*shco == IRTemp_INVALID); in mk_shifter_operand()
2334 vassert(rot <= 30); in mk_shifter_operand()
2359 vassert(shift_amt <= 31); in mk_shifter_operand()
2399 vassert(rN < 16); in mk_EA_reg_plusminus_imm12()
2400 vassert(bU < 2); in mk_EA_reg_plusminus_imm12()
2401 vassert(imm12 < 0x1000); in mk_EA_reg_plusminus_imm12()
2419 vassert(rN < 16); in mk_EA_reg_plusminus_shifted_reg()
2420 vassert(bU < 2); in mk_EA_reg_plusminus_shifted_reg()
2421 vassert(rM < 16); in mk_EA_reg_plusminus_shifted_reg()
2422 vassert(sh2 < 4); in mk_EA_reg_plusminus_shifted_reg()
2423 vassert(imm5 < 32); in mk_EA_reg_plusminus_shifted_reg()
2435 vassert(0); // ATC in mk_EA_reg_plusminus_shifted_reg()
2447 vassert(0); // ATC in mk_EA_reg_plusminus_shifted_reg()
2467 vassert(imm5 >= 1 && imm5 <= 31); in mk_EA_reg_plusminus_shifted_reg()
2475 vassert(0); in mk_EA_reg_plusminus_shifted_reg()
2477 vassert(index); in mk_EA_reg_plusminus_shifted_reg()
2488 vassert(rN < 16); in mk_EA_reg_plusminus_imm8()
2489 vassert(bU < 2); in mk_EA_reg_plusminus_imm8()
2490 vassert(imm8 < 0x100); in mk_EA_reg_plusminus_imm8()
2505 vassert(rN < 16); in mk_EA_reg_plusminus_reg()
2506 vassert(bU < 2); in mk_EA_reg_plusminus_reg()
2507 vassert(rM < 16); in mk_EA_reg_plusminus_reg()
2598 vassert(imm1 < (1<<1)); in thumbExpandImm()
2599 vassert(imm3 < (1<<3)); in thumbExpandImm()
2600 vassert(imm8 < (1<<8)); in thumbExpandImm()
2622 /*NOTREACHED*/vassert(0); in thumbExpandImm()
2668 vassert(firstcond <= 0xF); in compute_ITSTATE()
2669 vassert(mask <= 0xF); in compute_ITSTATE()
2926 vassert(0); in binop_w_fake_RM()
3119 default: vassert(0); in dis_neon_data_3same()
3143 vassert(0); in dis_neon_data_3same()
3160 vassert(0); in dis_neon_data_3same()
3200 vassert(0); in dis_neon_data_3same()
3221 vassert(0); in dis_neon_data_3same()
3251 default: vassert(0); in dis_neon_data_3same()
3270 vassert(0); in dis_neon_data_3same()
3289 vassert(0); in dis_neon_data_3same()
3412 vassert(0); in dis_neon_data_3same()
3511 vassert(0); in dis_neon_data_3same()
3532 default: vassert(0); in dis_neon_data_3same()
3558 vassert(0); in dis_neon_data_3same()
3575 vassert(0); in dis_neon_data_3same()
3615 vassert(0); in dis_neon_data_3same()
3636 vassert(0); in dis_neon_data_3same()
3660 default: vassert(0); in dis_neon_data_3same()
3668 default: vassert(0); in dis_neon_data_3same()
3705 default: vassert(0); in dis_neon_data_3same()
3727 vassert(0); in dis_neon_data_3same()
3788 vassert(0); in dis_neon_data_3same()
3817 vassert(0); in dis_neon_data_3same()
3893 default: vassert(0); in dis_neon_data_3same()
3925 vassert(0); in dis_neon_data_3same()
3954 vassert(0); in dis_neon_data_3same()
4031 default: vassert(0); in dis_neon_data_3same()
4067 vassert(0); in dis_neon_data_3same()
4100 vassert(0); in dis_neon_data_3same()
4187 default: vassert(0); in dis_neon_data_3same()
4195 default: vassert(0); in dis_neon_data_3same()
4212 default: vassert(0); in dis_neon_data_3same()
4220 default: vassert(0); in dis_neon_data_3same()
4255 vassert(0); in dis_neon_data_3same()
4274 vassert(0); in dis_neon_data_3same()
4324 vassert(0); in dis_neon_data_3same()
4346 vassert(0); in dis_neon_data_3same()
4388 default: vassert(0); in dis_neon_data_3same()
4400 default: vassert(0); in dis_neon_data_3same()
4414 default: vassert(0); in dis_neon_data_3same()
4459 vassert(0); in dis_neon_data_3same()
4478 vassert(0); in dis_neon_data_3same()
4498 default: vassert(0); in dis_neon_data_3same()
4506 default: vassert(0); in dis_neon_data_3same()
4528 default: vassert(0); in dis_neon_data_3same()
4536 default: vassert(0); in dis_neon_data_3same()
4569 vassert(0); in dis_neon_data_3same()
4603 vassert(0); in dis_neon_data_3same()
4628 default: vassert(0); in dis_neon_data_3same()
4700 default: vassert(0); in dis_neon_data_3same()
4709 default: vassert(0); in dis_neon_data_3same()
4861 vassert(0); in dis_neon_data_3same()
4917 vassert(0); in dis_neon_data_3diff()
4970 vassert(0); in dis_neon_data_3diff()
5020 vassert(0); in dis_neon_data_3diff()
5080 vassert(0); in dis_neon_data_3diff()
5127 vassert(0); in dis_neon_data_3diff()
5171 vassert(0); in dis_neon_data_3diff()
5209 vassert(0); in dis_neon_data_3diff()
5250 vassert(0); in dis_neon_data_3diff()
5283 vassert(0); in dis_neon_data_3diff()
5347 vassert(0); in dis_neon_data_2reg_and_scalar()
5372 vassert(0); in dis_neon_data_2reg_and_scalar()
5388 vassert(0); in dis_neon_data_2reg_and_scalar()
5406 vassert(0); in dis_neon_data_2reg_and_scalar()
5451 vassert(0); in dis_neon_data_2reg_and_scalar()
5469 vassert(0); in dis_neon_data_2reg_and_scalar()
5510 vassert(0); in dis_neon_data_2reg_and_scalar()
5535 vassert(0); in dis_neon_data_2reg_and_scalar()
5584 vassert(0); in dis_neon_data_2reg_and_scalar()
5609 vassert(0); in dis_neon_data_2reg_and_scalar()
5623 vassert(0); in dis_neon_data_2reg_and_scalar()
5637 vassert(0); in dis_neon_data_2reg_and_scalar()
5679 vassert(0); in dis_neon_data_2reg_and_scalar()
5686 default: vassert(0); in dis_neon_data_2reg_and_scalar()
5723 vassert(0); in dis_neon_data_2reg_and_scalar()
5744 vassert(0); in dis_neon_data_2reg_and_scalar()
5789 vassert(0); in dis_neon_data_2reg_and_scalar()
5814 vassert(0); in dis_neon_data_2reg_and_scalar()
5836 vassert(0); in dis_neon_data_2reg_and_scalar()
5887 vassert(0); in dis_neon_data_2reg_and_scalar()
5912 vassert(0); in dis_neon_data_2reg_and_scalar()
5934 vassert(0); in dis_neon_data_2reg_and_scalar()
6018 vassert(0); in dis_neon_data_2reg_and_shift()
6043 vassert(0); in dis_neon_data_2reg_and_shift()
6068 vassert(0); in dis_neon_data_2reg_and_shift()
6142 vassert(0); in dis_neon_data_2reg_and_shift()
6163 vassert(0); in dis_neon_data_2reg_and_shift()
6203 default: vassert(0); in dis_neon_data_2reg_and_shift()
6252 default: vassert(0); in dis_neon_data_2reg_and_shift()
6298 default: vassert(0); in dis_neon_data_2reg_and_shift()
6337 vassert(0); in dis_neon_data_2reg_and_shift()
6361 vassert(0); in dis_neon_data_2reg_and_shift()
6388 vassert(0); in dis_neon_data_2reg_and_shift()
6443 vassert(0); in dis_neon_data_2reg_and_shift()
6466 default: vassert(0); in dis_neon_data_2reg_and_shift()
6486 vassert(0); in dis_neon_data_2reg_and_shift()
6536 vassert(0); in dis_neon_data_2reg_and_shift()
6541 vassert(U); in dis_neon_data_2reg_and_shift()
6559 vassert(0); in dis_neon_data_2reg_and_shift()
6571 case 0: default: vassert(0); in dis_neon_data_2reg_and_shift()
6577 case 0: default: vassert(0); in dis_neon_data_2reg_and_shift()
6627 vassert(0); in dis_neon_data_2reg_and_shift()
6721 vassert(0); in dis_neon_data_2reg_misc()
6742 vassert(0); in dis_neon_data_2reg_misc()
6761 vassert(0); in dis_neon_data_2reg_misc()
6781 default: vassert(0); in dis_neon_data_2reg_misc()
6789 default: vassert(0); in dis_neon_data_2reg_misc()
6808 default: vassert(0); in dis_neon_data_2reg_misc()
6823 default: vassert(0); in dis_neon_data_2reg_misc()
6867 vassert(0); in dis_neon_data_2reg_misc()
6886 vassert(0); in dis_neon_data_2reg_misc()
6938 vassert(0); in dis_neon_data_2reg_misc()
6989 vassert(0); in dis_neon_data_2reg_misc()
6999 vassert(0); in dis_neon_data_2reg_misc()
7031 default: vassert(0); in dis_neon_data_2reg_misc()
7039 default: vassert(0); in dis_neon_data_2reg_misc()
7060 default: vassert(0); in dis_neon_data_2reg_misc()
7069 default: vassert(0); in dis_neon_data_2reg_misc()
7091 default: vassert(0); in dis_neon_data_2reg_misc()
7100 default: vassert(0); in dis_neon_data_2reg_misc()
7122 default: vassert(0); in dis_neon_data_2reg_misc()
7131 default: vassert(0); in dis_neon_data_2reg_misc()
7153 default: vassert(0); in dis_neon_data_2reg_misc()
7162 default: vassert(0); in dis_neon_data_2reg_misc()
7181 default: vassert(0); in dis_neon_data_2reg_misc()
7201 default: vassert(0); in dis_neon_data_2reg_misc()
7215 default: vassert(0); in dis_neon_data_2reg_misc()
7225 vassert(0); in dis_neon_data_2reg_misc()
7286 vassert(0); in dis_neon_data_2reg_misc()
7305 vassert(0); in dis_neon_data_2reg_misc()
7357 vassert(0); in dis_neon_data_2reg_misc()
7408 vassert(0); in dis_neon_data_2reg_misc()
7431 default: vassert(0); in dis_neon_data_2reg_misc()
7450 default: vassert(0); in dis_neon_data_2reg_misc()
7454 vassert(0); in dis_neon_data_2reg_misc()
7461 default: vassert(0); in dis_neon_data_2reg_misc()
7471 default: vassert(0); in dis_neon_data_2reg_misc()
7481 default: vassert(0); in dis_neon_data_2reg_misc()
7486 vassert(0); in dis_neon_data_2reg_misc()
7511 default: vassert(0); in dis_neon_data_2reg_misc()
7521 vassert(0); // ATC in dis_neon_data_2reg_misc()
7543 vassert(0); in dis_neon_data_2reg_misc()
7610 vassert(0); in dis_neon_data_2reg_misc()
7621 vassert(0); in dis_neon_data_2reg_misc()
7624 vassert(0); in dis_neon_data_2reg_misc()
7684 vassert(0); in ppNeonImmType()
7688 vassert(0); in ppNeonImmType()
7908 vassert(0); in mk_neon_elem_load_to_one_lane()
7943 vassert(0); in mk_neon_elem_load_to_one_lane()
7969 vassert(0); in mk_neon_elem_store_from_one_lane()
7989 vassert(0); in mk_neon_elem_store_from_one_lane()
8002 vassert(u0 && u1); in math_DEINTERLEAVE_2()
8038 vassert(i0 && i1); in math_INTERLEAVE_2()
8078 vassert(desc[2 * si + 0] <= 2); in math_PERM_8x8x3()
8079 vassert(desc[2 * si + 1] <= 7); in math_PERM_8x8x3()
8125 vassert(u0 && u1 && u2); in math_DEINTERLEAVE_3()
8180 vassert(i0 && i1 && i2); in math_INTERLEAVE_3()
8245 vassert(u0 && u1 && u2 && u3); in math_DEINTERLEAVE_4()
8325 vassert(u0 && u1 && u2 && u3); in math_INTERLEAVE_4()
8400 vassert(condT != IRTemp_INVALID); in dis_neon_load_or_store()
8402 vassert(condT == IRTemp_INVALID); in dis_neon_load_or_store()
8434 default: vassert(0); in dis_neon_load_or_store()
8511 vassert(0); in dis_neon_load_or_store()
8540 vassert(0); in dis_neon_load_or_store()
8642 vassert(regs == 1 || regs == 2 || regs == 3 || regs == 4); in dis_neon_load_or_store()
8656 vassert( (regs == 1 && (inc == 1 || inc == 2)) in dis_neon_load_or_store()
8673 vassert(0); in dis_neon_load_or_store()
8701 vassert(nregs == 4); in dis_neon_load_or_store()
8702 vassert(regstep == 1); in dis_neon_load_or_store()
8750 vassert(regs == 1 && (inc == 1 || inc == 2)); in dis_neon_load_or_store()
8785 vassert(regs == 1 && (inc == 1 || inc == 2)); in dis_neon_load_or_store()
8826 vassert(0); in dis_neon_load_or_store()
8916 vassert(condT == IRTemp_INVALID); in decode_NEON_instruction_ARMv7_and_below()
9001 vassert(conq == ARMCondAL); in decode_V6MEDIA_instruction()
9003 vassert(INSNA(31,28) == BITS4(0,0,0,0)); // caller's obligation in decode_V6MEDIA_instruction()
9004 vassert(conq >= ARMCondEQ && conq <= ARMCondAL); in decode_V6MEDIA_instruction()
12655 vassert(t0 && *t0 == IRTemp_INVALID); in breakupV128to32s()
12656 vassert(t1 && *t1 == IRTemp_INVALID); in breakupV128to32s()
12657 vassert(t2 && *t2 == IRTemp_INVALID); in breakupV128to32s()
12658 vassert(t3 && *t3 == IRTemp_INVALID); in breakupV128to32s()
12710 vassert(old_itstate != IRTemp_INVALID); in decode_V8_instruction()
12711 vassert(new_itstate != IRTemp_INVALID); in decode_V8_instruction()
12713 vassert(old_itstate == IRTemp_INVALID); in decode_V8_instruction()
12714 vassert(new_itstate == IRTemp_INVALID); in decode_V8_instruction()
12728 vassert(condT == IRTemp_INVALID); in decode_V8_instruction()
12730 vassert(condT != IRTemp_INVALID); in decode_V8_instruction()
12732 vassert(conq >= ARMCondEQ && conq <= ARMCondNV); in decode_V8_instruction()
12797 vassert(opc >= 0 && opc <= 3); in decode_V8_instruction()
12874 vassert(ix >= 0 && ix < 7); in decode_V8_instruction()
12937 vassert(0); in decode_V8_instruction()
13206 default: /*NOTREACHED*/vassert(0); in decode_V8_instruction()
13219 vassert(szBlg2 <= 2 && nn <= 14 && tt <= 14); in decode_V8_instruction()
13239 default: vassert(0); in decode_V8_instruction()
13327 default: /*NOTREACHED*/vassert(0); in decode_V8_instruction()
13359 vassert(tt2 == 16/*invalid*/); in decode_V8_instruction()
13371 vassert(tt2 == 16/*invalid*/); in decode_V8_instruction()
13375 else /*NOTREACHED*/vassert(0); in decode_V8_instruction()
13379 vassert(szBlg2 <= 3); in decode_V8_instruction()
13380 if (szBlg2 < 3) { vassert(tt2 == 16/*invalid*/); } in decode_V8_instruction()
13381 else { vassert(tt2 <= 14); } in decode_V8_instruction()
13382 if (isLoad) { vassert(dd == 16/*invalid*/); } in decode_V8_instruction()
13383 else { vassert(dd <= 14); } in decode_V8_instruction()
13389 vassert(condT != IRTemp_INVALID); in decode_V8_instruction()
13405 default: vassert(0); in decode_V8_instruction()
13415 default: vassert(0); in decode_V8_instruction()
13422 do { vassert((_nnz) <= 14); /* no writes to the PC */ \ in decode_V8_instruction()
13450 default: vassert(0); in decode_V8_instruction()
13472 vassert(dd <= 14); /* no writes to the PC */ in decode_V8_instruction()
13576 default: vassert(0); in decode_V8_instruction()
13612 if (isT) vassert(condT != IRTemp_INVALID); in decode_V8_instruction()
13671 default: vassert(0); in decode_V8_instruction()
13762 if (isT) vassert(condT != IRTemp_INVALID); in decode_V8_instruction()
13906 default: vassert(0); in decode_V8_instruction()
14002 default: vassert(0); in decode_V8_instruction()
14125 vassert(r != rN); in mk_ldm_stm()
14134 vassert(m == nRegs); in mk_ldm_stm()
14135 vassert(nX == nRegs); in mk_ldm_stm()
14136 vassert(nX <= 16); in mk_ldm_stm()
14149 vassert(nX > 0); in mk_ldm_stm()
14154 vassert(i < nX); /* else we didn't find it! */ in mk_ldm_stm()
14164 vassert(m == nX); in mk_ldm_stm()
14175 vassert(m == -1); in mk_ldm_stm()
14282 vassert(INSN(31,28) == BITS4(0,0,0,0)); // caller's obligation in decode_CP10_CP11_instruction()
14285 vassert(conq == ARMCondAL); in decode_CP10_CP11_instruction()
14287 vassert(conq >= ARMCondEQ && conq <= ARMCondAL); in decode_CP10_CP11_instruction()
14422 default: vassert(0); in decode_CP10_CP11_instruction()
14559 default: vassert(0); in decode_CP10_CP11_instruction()
14865 vassert(0); in decode_CP10_CP11_instruction()
14882 vassert(0); in decode_CP10_CP11_instruction()
15153 vassert(0); in decode_CP10_CP11_instruction()
15351 default: vassert(0); in decode_CP10_CP11_instruction()
15667 vassert(0); in decode_CP10_CP11_instruction()
15903 vassert(INSN(11,9) == BITS3(1,0,1)); // 11:8 = 1010 or 1011 in decode_CP10_CP11_instruction()
15934 vassert(BITS4(1,1,1,1) == INSN_COND); in decode_NV_instruction_ARMv7_and_below()
15963 vassert(eaE); in decode_NV_instruction_ARMv7_and_below()
16119 vassert(0 == (guest_R15_curr_instr_notENC & 3)); in disInstr_ARM_WRK()
16273 vassert(op == Iop_Sub32); isRSB = True; break; in disInstr_ARM_WRK()
16275 vassert(op == Iop_And32); isBIC = True; break; in disInstr_ARM_WRK()
16291 vassert(op == Iop_Sub32); in disInstr_ARM_WRK()
16295 vassert(op == Iop_And32); in disInstr_ARM_WRK()
16315 vassert(shco == IRTemp_INVALID); in disInstr_ARM_WRK()
16318 vassert(shco != IRTemp_INVALID); in disInstr_ARM_WRK()
16338 vassert(0); in disInstr_ARM_WRK()
16363 vassert(shco != IRTemp_INVALID); in disInstr_ARM_WRK()
16367 vassert(shco == IRTemp_INVALID); in disInstr_ARM_WRK()
16485 vassert(0); in disInstr_ARM_WRK()
16494 vassert(shco == IRTemp_INVALID); in disInstr_ARM_WRK()
16497 vassert(shco != IRTemp_INVALID); in disInstr_ARM_WRK()
16512 vassert(0); in disInstr_ARM_WRK()
16521 vassert(0); in disInstr_ARM_WRK()
16603 vassert(0); in disInstr_ARM_WRK()
16618 vassert(eaE); in disInstr_ARM_WRK()
16632 vassert(taT != IRTemp_INVALID); in disInstr_ARM_WRK()
16659 vassert(bB == 1); in disInstr_ARM_WRK()
16665 vassert(bL == 1); in disInstr_ARM_WRK()
16694 vassert(bB == 1); in disInstr_ARM_WRK()
16707 vassert(rD != rN); /* since we just wrote rD */ in disInstr_ARM_WRK()
16726 default: vassert(0); in disInstr_ARM_WRK()
16842 vassert(0); in disInstr_ARM_WRK()
16868 vassert(eaE); in disInstr_ARM_WRK()
16882 vassert(taT != IRTemp_INVALID); in disInstr_ARM_WRK()
16922 vassert(0); // should be assured by logic above in disInstr_ARM_WRK()
16929 vassert(rD != rN); /* since we just wrote rD */ in disInstr_ARM_WRK()
16943 default: vassert(0); in disInstr_ARM_WRK()
17287 vassert(!isMLS); // guaranteed above in disInstr_ARM_WRK()
17461 vassert(rot <= 30); in disInstr_ARM_WRK()
17593 default: vassert(0); in disInstr_ARM_WRK()
17599 vassert(ty == Ity_I64); in disInstr_ARM_WRK()
17648 default: vassert(0); in disInstr_ARM_WRK()
17655 vassert(ty == Ity_I64); in disInstr_ARM_WRK()
17786 vassert(0); // guarded by "if" above in disInstr_ARM_WRK()
17810 vassert(mask != 0); // guaranteed by "msb < lsb" check above in disInstr_ARM_WRK()
17855 vassert(msb >= 0 && msb <= 31); in disInstr_ARM_WRK()
17856 vassert(mask != 0); // guaranteed by msb being in 0 .. 31 inclusive in disInstr_ARM_WRK()
17962 vassert(0); in disInstr_ARM_WRK()
17968 vassert((rD & 1) == 0); /* from tests above */ in disInstr_ARM_WRK()
17987 vassert(eaE); in disInstr_ARM_WRK()
18001 vassert(taT != IRTemp_INVALID); in disInstr_ARM_WRK()
18056 vassert(rN != 15); /* from checks above */ in disInstr_ARM_WRK()
18058 vassert(rD+0 != rN); /* since we just wrote rD+0 */ in disInstr_ARM_WRK()
18059 vassert(rD+1 != rN); /* since we just wrote rD+1 */ in disInstr_ARM_WRK()
18075 default: vassert(0); in disInstr_ARM_WRK()
18863 vassert(0 == (guest_R15_curr_instr_notENC & 3)); in disInstr_ARM_WRK()
18875 vassert(dres.len == 4 || dres.len == 20); in disInstr_ARM_WRK()
18889 vassert(dres.whatNext == Dis_Continue); in disInstr_ARM_WRK()
18890 vassert(irsb->next == NULL); in disInstr_ARM_WRK()
18891 vassert(irsb->jumpkind == Ijk_Boring); in disInstr_ARM_WRK()
18932 vassert(0); in disInstr_ARM_WRK()
19013 vassert(0 == (guest_R15_curr_instr_notENC & 1)); in disInstr_THUMB_WRK()
19140 vassert(guaranteedUnconditional == False); in disInstr_THUMB_WRK()
19143 vassert(0 == (pc & 1)); in disInstr_THUMB_WRK()
19174 vassert(n_guarded >= 1 && n_guarded <= 4); in disInstr_THUMB_WRK()
19208 vassert(old_itstate == IRTemp_INVALID); in disInstr_THUMB_WRK()
19670 /*NOTREACHED*/vassert(0); in disInstr_THUMB_WRK()
19767 vassert(rM == 15); in disInstr_THUMB_WRK()
19959 vassert(0 == (guest_R15_curr_instr_notENC & 1)); in disInstr_THUMB_WRK()
20011 vassert(nRegs >= 1 && nRegs <= 9); in disInstr_THUMB_WRK()
20065 vassert(nRegs >= 0 && nRegs <= 8); in disInstr_THUMB_WRK()
20066 vassert(bitR == 0 || bitR == 1); in disInstr_THUMB_WRK()
20612 /*NOTREACHED*/vassert(0); in disInstr_THUMB_WRK()
20724 vassert(insn1 == 0); in disInstr_THUMB_WRK()
20731 vassert(dres.whatNext == Dis_Continue); in disInstr_THUMB_WRK()
20732 vassert(dres.len == 2); in disInstr_THUMB_WRK()
20733 vassert(dres.continueAt == 0); in disInstr_THUMB_WRK()
20754 vassert(0 == (guest_R15_curr_instr_notENC & 1)); in disInstr_THUMB_WRK()
21073 vassert(0); in disInstr_THUMB_WRK()
21107 default: vassert(0); in disInstr_THUMB_WRK()
21171 default: vassert(0); in disInstr_THUMB_WRK()
21203 vassert(0); in disInstr_THUMB_WRK()
21269 vassert(0); in disInstr_THUMB_WRK()
21305 default: vassert(0); in disInstr_THUMB_WRK()
21326 vassert(op == Iop_And32 || op == Iop_Or32); in disInstr_THUMB_WRK()
21671 vassert(rN != rT); // assured by validity check above in disInstr_THUMB_WRK()
21688 vassert(0); in disInstr_THUMB_WRK()
21709 vassert(0); in disInstr_THUMB_WRK()
21714 vassert(loadsPC); in disInstr_THUMB_WRK()
21717 vassert(!loadsPC); in disInstr_THUMB_WRK()
21726 vassert(rN != rT); // assured by validity check above in disInstr_THUMB_WRK()
21732 vassert(rN != 15); // assured by validity check above in disInstr_THUMB_WRK()
21733 vassert(rT == 15); in disInstr_THUMB_WRK()
21734 vassert(condT == IRTemp_INVALID); /* due to check above */ in disInstr_THUMB_WRK()
21750 vassert(bP == 0 && bW == 1); in disInstr_THUMB_WRK()
21807 vassert(ty == Ity_I32); in disInstr_THUMB_WRK()
21856 vassert(0); in disInstr_THUMB_WRK()
21877 vassert(0); in disInstr_THUMB_WRK()
21883 vassert(loadsPC); in disInstr_THUMB_WRK()
21886 vassert(!loadsPC); in disInstr_THUMB_WRK()
21895 vassert(rN != 15); // assured by validity check above in disInstr_THUMB_WRK()
21896 vassert(rT == 15); in disInstr_THUMB_WRK()
21897 vassert(condT == IRTemp_INVALID); /* due to check above */ in disInstr_THUMB_WRK()
21987 vassert(!isST); in disInstr_THUMB_WRK()
22017 vassert(0); in disInstr_THUMB_WRK()
22031 vassert(0); in disInstr_THUMB_WRK()
22036 vassert(loadsPC); in disInstr_THUMB_WRK()
22039 vassert(!loadsPC); in disInstr_THUMB_WRK()
22048 vassert(rT == 15); in disInstr_THUMB_WRK()
22049 vassert(condT == IRTemp_INVALID); /* due to check above */ in disInstr_THUMB_WRK()
22159 vassert(bP == 0 && bW == 1); in disInstr_THUMB_WRK()
22186 vassert(0 == (guest_R15_curr_instr_notENC & 1)); in disInstr_THUMB_WRK()
22232 vassert(0 == (guest_R15_curr_instr_notENC & 1)); in disInstr_THUMB_WRK()
22313 vassert(msb >= 0 && msb <= 31); in disInstr_THUMB_WRK()
22314 vassert(mask != 0); // guaranteed by msb being in 0 .. 31 inclusive in disInstr_THUMB_WRK()
22405 vassert(0); in disInstr_THUMB_WRK()
22674 vassert(mask != 0); // guaranteed by "msb < lsb" check above in disInstr_THUMB_WRK()
23472 vassert(0 == (guest_R15_curr_instr_notENC & 1)); in disInstr_THUMB_WRK()
23482 vassert(dres.len == 4 || dres.len == 2 || dres.len == 20); in disInstr_THUMB_WRK()
23494 vassert(0); in disInstr_THUMB_WRK()
23612 vassert(guest_arch == VexArchARM); in disInstr_ARM()