98           && e->Iex.Const.con->Ico.U8 == 0;  in isZeroU8()
298           && e->Iex.Const.con->Ico.U64 == 0ULL;  in isZeroU64()
305           && e->Iex.Const.con->Ico.U32 == 0;  in isZeroU32()
381       if (fitsIn32Bits(e->Iex.Const.con->Ico.U64)) {  in iselIntExpr_single_instruction()
384                    AMD64RMI_Imm(toUInt(e->Iex.Const.con->Ico.U64)),  in iselIntExpr_single_instruction()
388          return AMD64Instr_Imm64(e->Iex.Const.con->Ico.U64, dst);  in iselIntExpr_single_instruction()
542           && guard->Iex.Const.con->Ico.U1 == True) {  in doHelperCall()
639           && guard->Iex.Const.con->Ico.U1 == True) {  in doHelperCall()
1066             nshift = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8;  in iselIntExpr_R_wrk()
1850          addInstr(env, AMD64Instr_Imm64(e->Iex.Const.con->Ico.U64, r));  in iselIntExpr_R_wrk()
1970           && imm8->Iex.Const.con->Ico.U8 < 4  in iselIntExpr_AMode_wrk()
1974           && fitsIn32Bits(simm32->Iex.Const.con->Ico.U64)) {  in iselIntExpr_AMode_wrk()
1975          UInt shift = imm8->Iex.Const.con->Ico.U8;  in iselIntExpr_AMode_wrk()
1976          UInt offset = toUInt(simm32->Iex.Const.con->Ico.U64);  in iselIntExpr_AMode_wrk()
1991       UInt shift = e->Iex.Binop.arg2->Iex.Binop.arg2->Iex.Const.con->Ico.U8;  in iselIntExpr_AMode_wrk()
2004        && fitsIn32Bits(e->Iex.Binop.arg2->Iex.Const.con->Ico.U64)) {  in iselIntExpr_AMode_wrk()
2007                 toUInt(e->Iex.Binop.arg2->Iex.Const.con->Ico.U64),   in iselIntExpr_AMode_wrk()
2056            if (fitsIn32Bits(e->Iex.Const.con->Ico.U64)) {  in iselIntExpr_RMI_wrk()
2057               return AMD64RMI_Imm(toUInt(e->Iex.Const.con->Ico.U64));  in iselIntExpr_RMI_wrk()
2061             return AMD64RMI_Imm(e->Iex.Const.con->Ico.U32); break;  in iselIntExpr_RMI_wrk()
2063             return AMD64RMI_Imm(0xFFFF & e->Iex.Const.con->Ico.U16); break;  in iselIntExpr_RMI_wrk()
2065             return AMD64RMI_Imm(0xFF & e->Iex.Const.con->Ico.U8); break;  in iselIntExpr_RMI_wrk()
2125            if (fitsIn32Bits(e->Iex.Const.con->Ico.U64)) {  in iselIntExpr_RI_wrk()
2126               return AMD64RI_Imm(toUInt(e->Iex.Const.con->Ico.U64));  in iselIntExpr_RI_wrk()
2130             return AMD64RI_Imm(e->Iex.Const.con->Ico.U32);  in iselIntExpr_RI_wrk()
2132             return AMD64RI_Imm(0xFFFF & e->Iex.Const.con->Ico.U16);  in iselIntExpr_RI_wrk()
2134             return AMD64RI_Imm(0xFF & e->Iex.Const.con->Ico.U8);  in iselIntExpr_RI_wrk()
2226       vassert(e->Iex.Const.con->Ico.U1 == True   in iselCondCode_wrk()
2227               || e->Iex.Const.con->Ico.U1 == False);  in iselCondCode_wrk()
2231       return e->Iex.Const.con->Ico.U1 ? Acc_Z : Acc_NZ;  in iselCondCode_wrk()
2387       addInstr(env, AMD64Instr_Imm64(con->Iex.Const.con->Ico.U64, tmp));  in iselCondCode_wrk()
2771          u.f64 = e->Iex.Const.con->Ico.F64;  in iselDblExpr_wrk()
2774          u.u64 = e->Iex.Const.con->Ico.F64i;  in iselDblExpr_wrk()
3155       switch (e->Iex.Const.con->Ico.V128) {  in iselVecExpr_wrk()
3166                                 (e->Iex.Const.con->Ico.V128 >> 8) & 0xFF  in iselVecExpr_wrk()
3169                                 (e->Iex.Const.con->Ico.V128 >> 0) & 0xFF  in iselVecExpr_wrk()
3780       switch (e->Iex.Const.con->Ico.V256) {  in iselDVecExpr_wrk()
4776                = ((Addr64)stmt->Ist.Exit.dst->Ico.U64) > env->max_ga;  in iselStmt()
4778             addInstr(env, AMD64Instr_XDirect(stmt->Ist.Exit.dst->Ico.U64,  in iselStmt()
4851                = ((Addr64)cdst->Ico.U64) > env->max_ga;  in iselNext()
4853             addInstr(env, AMD64Instr_XDirect(cdst->Ico.U64,   in iselNext()