Lines Matching refs:Iex
97 && e->Iex.Const.con->tag == Ico_U8 in isZeroU8()
98 && e->Iex.Const.con->Ico.U8 == 0; in isZeroU8()
297 && e->Iex.Const.con->tag == Ico_U64 in isZeroU64()
298 && e->Iex.Const.con->Ico.U64 == 0ULL; in isZeroU64()
304 && e->Iex.Const.con->tag == Ico_U32 in isZeroU32()
305 && e->Iex.Const.con->Ico.U32 == 0; in isZeroU32()
380 vassert(e->Iex.Const.con->tag == Ico_U64); in iselIntExpr_single_instruction()
381 if (fitsIn32Bits(e->Iex.Const.con->Ico.U64)) { in iselIntExpr_single_instruction()
384 AMD64RMI_Imm(toUInt(e->Iex.Const.con->Ico.U64)), in iselIntExpr_single_instruction()
388 return AMD64Instr_Imm64(e->Iex.Const.con->Ico.U64, dst); in iselIntExpr_single_instruction()
393 HReg src = lookupIRTemp(env, e->Iex.RdTmp.tmp); in iselIntExpr_single_instruction()
398 vassert(e->Iex.Get.ty == Ity_I64); in iselIntExpr_single_instruction()
402 AMD64AMode_IR(e->Iex.Get.offset, in iselIntExpr_single_instruction()
408 && e->Iex.Unop.op == Iop_32Uto64 in iselIntExpr_single_instruction()
409 && e->Iex.Unop.arg->tag == Iex_RdTmp) { in iselIntExpr_single_instruction()
410 HReg src = lookupIRTemp(env, e->Iex.Unop.arg->Iex.RdTmp.tmp); in iselIntExpr_single_instruction()
541 && guard->Iex.Const.con->tag == Ico_U1 in doHelperCall()
542 && guard->Iex.Const.con->Ico.U1 == True) { in doHelperCall()
638 && guard->Iex.Const.con->tag == Ico_U1 in doHelperCall()
639 && guard->Iex.Const.con->Ico.U1 == True) { in doHelperCall()
933 return lookupIRTemp(env, e->Iex.RdTmp.tmp); in iselIntExpr_R_wrk()
939 AMD64AMode* amode = iselIntExpr_AMode ( env, e->Iex.Load.addr ); in iselIntExpr_R_wrk()
942 if (e->Iex.Load.end != Iend_LE) in iselIntExpr_R_wrk()
972 if ((e->Iex.Binop.op == Iop_Sub64 && isZeroU64(e->Iex.Binop.arg1)) in iselIntExpr_R_wrk()
973 || (e->Iex.Binop.op == Iop_Sub32 && isZeroU32(e->Iex.Binop.arg1))) { in iselIntExpr_R_wrk()
975 HReg reg = iselIntExpr_R(env, e->Iex.Binop.arg2); in iselIntExpr_R_wrk()
982 switch (e->Iex.Binop.op) { in iselIntExpr_R_wrk()
1002 HReg reg = iselIntExpr_R(env, e->Iex.Binop.arg1); in iselIntExpr_R_wrk()
1003 AMD64RMI* rmi = iselIntExpr_RMI(env, e->Iex.Binop.arg2); in iselIntExpr_R_wrk()
1010 switch (e->Iex.Binop.op) { in iselIntExpr_R_wrk()
1024 HReg regL = iselIntExpr_R(env, e->Iex.Binop.arg1); in iselIntExpr_R_wrk()
1028 switch (e->Iex.Binop.op) { in iselIntExpr_R_wrk()
1056 ppIROp(e->Iex.Binop.op); in iselIntExpr_R_wrk()
1062 if (e->Iex.Binop.arg2->tag == Iex_Const) { in iselIntExpr_R_wrk()
1065 vassert(e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U8); in iselIntExpr_R_wrk()
1066 nshift = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; in iselIntExpr_R_wrk()
1073 HReg regR = iselIntExpr_R(env, e->Iex.Binop.arg2); in iselIntExpr_R_wrk()
1082 switch (e->Iex.Binop.op) { in iselIntExpr_R_wrk()
1224 HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); in iselIntExpr_R_wrk()
1225 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); in iselIntExpr_R_wrk()
1238 if (e->Iex.Binop.op == Iop_Max32U) { in iselIntExpr_R_wrk()
1239 HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); in iselIntExpr_R_wrk()
1241 HReg src2 = iselIntExpr_R(env, e->Iex.Binop.arg2); in iselIntExpr_R_wrk()
1248 if (e->Iex.Binop.op == Iop_DivModS64to32 in iselIntExpr_R_wrk()
1249 || e->Iex.Binop.op == Iop_DivModU64to32) { in iselIntExpr_R_wrk()
1256 Bool syned = toBool(e->Iex.Binop.op == Iop_DivModS64to32); in iselIntExpr_R_wrk()
1257 AMD64RM* rmRight = iselIntExpr_RM(env, e->Iex.Binop.arg2); in iselIntExpr_R_wrk()
1260 HReg left64 = iselIntExpr_R(env, e->Iex.Binop.arg1); in iselIntExpr_R_wrk()
1273 if (e->Iex.Binop.op == Iop_32HLto64) { in iselIntExpr_R_wrk()
1276 HReg hi32s = iselIntExpr_R(env, e->Iex.Binop.arg1); in iselIntExpr_R_wrk()
1277 HReg lo32s = iselIntExpr_R(env, e->Iex.Binop.arg2); in iselIntExpr_R_wrk()
1287 if (e->Iex.Binop.op == Iop_16HLto32) { in iselIntExpr_R_wrk()
1290 HReg hi16s = iselIntExpr_R(env, e->Iex.Binop.arg1); in iselIntExpr_R_wrk()
1291 HReg lo16s = iselIntExpr_R(env, e->Iex.Binop.arg2); in iselIntExpr_R_wrk()
1302 if (e->Iex.Binop.op == Iop_8HLto16) { in iselIntExpr_R_wrk()
1305 HReg hi8s = iselIntExpr_R(env, e->Iex.Binop.arg1); in iselIntExpr_R_wrk()
1306 HReg lo8s = iselIntExpr_R(env, e->Iex.Binop.arg2); in iselIntExpr_R_wrk()
1317 if (e->Iex.Binop.op == Iop_MullS32 in iselIntExpr_R_wrk()
1318 || e->Iex.Binop.op == Iop_MullS16 in iselIntExpr_R_wrk()
1319 || e->Iex.Binop.op == Iop_MullS8 in iselIntExpr_R_wrk()
1320 || e->Iex.Binop.op == Iop_MullU32 in iselIntExpr_R_wrk()
1321 || e->Iex.Binop.op == Iop_MullU16 in iselIntExpr_R_wrk()
1322 || e->Iex.Binop.op == Iop_MullU8) { in iselIntExpr_R_wrk()
1325 HReg a32s = iselIntExpr_R(env, e->Iex.Binop.arg1); in iselIntExpr_R_wrk()
1326 HReg b32s = iselIntExpr_R(env, e->Iex.Binop.arg2); in iselIntExpr_R_wrk()
1329 switch (e->Iex.Binop.op) { in iselIntExpr_R_wrk()
1349 if (e->Iex.Binop.op == Iop_CmpF64) { in iselIntExpr_R_wrk()
1350 HReg fL = iselDblExpr(env, e->Iex.Binop.arg1); in iselIntExpr_R_wrk()
1351 HReg fR = iselDblExpr(env, e->Iex.Binop.arg2); in iselIntExpr_R_wrk()
1360 if (e->Iex.Binop.op == Iop_F64toI32S in iselIntExpr_R_wrk()
1361 || e->Iex.Binop.op == Iop_F64toI64S) { in iselIntExpr_R_wrk()
1362 Int szD = e->Iex.Binop.op==Iop_F64toI32S ? 4 : 8; in iselIntExpr_R_wrk()
1363 HReg rf = iselDblExpr(env, e->Iex.Binop.arg2); in iselIntExpr_R_wrk()
1365 set_SSE_rounding_mode( env, e->Iex.Binop.arg1 ); in iselIntExpr_R_wrk()
1421 if (e->Iex.Unop.op == Iop_32Uto64 && e->Iex.Unop.arg->tag == Iex_Binop) { in iselIntExpr_R_wrk()
1422 IROp opi = e->Iex.Unop.arg->Iex.Binop.op; /* inner op */ in iselIntExpr_R_wrk()
1423 IRExpr* argL = e->Iex.Unop.arg->Iex.Binop.arg1; in iselIntExpr_R_wrk()
1424 IRExpr* argR = e->Iex.Unop.arg->Iex.Binop.arg2; in iselIntExpr_R_wrk()
1448 switch (e->Iex.Unop.op) { in iselIntExpr_R_wrk()
1452 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); in iselIntExpr_R_wrk()
1453 addInstr(env, AMD64Instr_MovxLQ(e->Iex.Unop.op == Iop_32Sto64, in iselIntExpr_R_wrk()
1459 iselInt128Expr(&rHi,&rLo, env, e->Iex.Unop.arg); in iselIntExpr_R_wrk()
1464 iselInt128Expr(&rHi,&rLo, env, e->Iex.Unop.arg); in iselIntExpr_R_wrk()
1473 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); in iselIntExpr_R_wrk()
1474 Bool srcIs16 = toBool( e->Iex.Unop.op==Iop_16Uto32 in iselIntExpr_R_wrk()
1475 || e->Iex.Unop.op==Iop_16Uto64 ); in iselIntExpr_R_wrk()
1488 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); in iselIntExpr_R_wrk()
1489 Bool srcIs16 = toBool( e->Iex.Unop.op==Iop_16Sto32 in iselIntExpr_R_wrk()
1490 || e->Iex.Unop.op==Iop_16Sto64 ); in iselIntExpr_R_wrk()
1502 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); in iselIntExpr_R_wrk()
1511 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); in iselIntExpr_R_wrk()
1513 switch (e->Iex.Unop.op) { in iselIntExpr_R_wrk()
1527 AMD64CondCode cond = iselCondCode(env, e->Iex.Unop.arg); in iselIntExpr_R_wrk()
1537 AMD64CondCode cond = iselCondCode(env, e->Iex.Unop.arg); in iselIntExpr_R_wrk()
1546 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); in iselIntExpr_R_wrk()
1556 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); in iselIntExpr_R_wrk()
1567 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); in iselIntExpr_R_wrk()
1579 HReg pre = iselIntExpr_R(env, e->Iex.Unop.arg); in iselIntExpr_R_wrk()
1595 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); in iselIntExpr_R_wrk()
1604 HReg vec = iselVecExpr(env, e->Iex.Unop.arg); in iselIntExpr_R_wrk()
1615 Int off = e->Iex.Unop.op==Iop_V128HIto64 ? -8 : -16; in iselIntExpr_R_wrk()
1617 HReg vec = iselVecExpr(env, e->Iex.Unop.arg); in iselIntExpr_R_wrk()
1630 iselDVecExpr(&vHi, &vLo, env, e->Iex.Unop.arg); in iselIntExpr_R_wrk()
1635 switch (e->Iex.Unop.op) { in iselIntExpr_R_wrk()
1659 HReg src = iselDblExpr(env, e->Iex.Unop.arg); in iselIntExpr_R_wrk()
1674 HReg src = iselFltExpr(env, e->Iex.Unop.arg); in iselIntExpr_R_wrk()
1689 return iselIntExpr_R(env, e->Iex.Unop.arg); in iselIntExpr_R_wrk()
1697 HReg arg = iselIntExpr_R(env, e->Iex.Unop.arg); in iselIntExpr_R_wrk()
1716 HReg vec = iselVecExpr(env, e->Iex.Unop.arg); in iselIntExpr_R_wrk()
1747 switch (e->Iex.Unop.op) { in iselIntExpr_R_wrk()
1764 HReg arg = iselIntExpr_R(env, e->Iex.Unop.arg); in iselIntExpr_R_wrk()
1782 AMD64AMode_IR(e->Iex.Get.offset, in iselIntExpr_R_wrk()
1792 AMD64AMode_IR(e->Iex.Get.offset,hregAMD64_RBP()), in iselIntExpr_R_wrk()
1802 env, e->Iex.GetI.descr, in iselIntExpr_R_wrk()
1803 e->Iex.GetI.ix, e->Iex.GetI.bias ); in iselIntExpr_R_wrk()
1819 vassert(ty == e->Iex.CCall.retty); in iselIntExpr_R_wrk()
1823 if (e->Iex.CCall.retty != Ity_I64 && e->Iex.CCall.retty != Ity_I32) in iselIntExpr_R_wrk()
1830 e->Iex.CCall.cee, e->Iex.CCall.retty, e->Iex.CCall.args ); in iselIntExpr_R_wrk()
1837 if (e->Iex.CCall.retty == Ity_I64) in iselIntExpr_R_wrk()
1850 addInstr(env, AMD64Instr_Imm64(e->Iex.Const.con->Ico.U64, r)); in iselIntExpr_R_wrk()
1862 && typeOfIRExpr(env->type_env,e->Iex.ITE.cond) == Ity_I1) { in iselIntExpr_R_wrk()
1863 HReg r1 = iselIntExpr_R(env, e->Iex.ITE.iftrue); in iselIntExpr_R_wrk()
1864 HReg r0 = iselIntExpr_R(env, e->Iex.ITE.iffalse); in iselIntExpr_R_wrk()
1867 AMD64CondCode cc = iselCondCode(env, e->Iex.ITE.cond); in iselIntExpr_R_wrk()
1876 IRTriop *triop = e->Iex.Triop.details; in iselIntExpr_R_wrk()
1969 && imm8->Iex.Const.con->tag == Ico_U8 in iselIntExpr_AMode_wrk()
1970 && imm8->Iex.Const.con->Ico.U8 < 4 in iselIntExpr_AMode_wrk()
1973 && simm32->Iex.Const.con->tag == Ico_U64 in iselIntExpr_AMode_wrk()
1974 && fitsIn32Bits(simm32->Iex.Const.con->Ico.U64)) { in iselIntExpr_AMode_wrk()
1975 UInt shift = imm8->Iex.Const.con->Ico.U8; in iselIntExpr_AMode_wrk()
1976 UInt offset = toUInt(simm32->Iex.Const.con->Ico.U64); in iselIntExpr_AMode_wrk()
1986 && e->Iex.Binop.op == Iop_Add64 in iselIntExpr_AMode_wrk()
1987 && e->Iex.Binop.arg2->tag == Iex_Binop in iselIntExpr_AMode_wrk()
1988 && e->Iex.Binop.arg2->Iex.Binop.op == Iop_Shl64 in iselIntExpr_AMode_wrk()
1989 && e->Iex.Binop.arg2->Iex.Binop.arg2->tag == Iex_Const in iselIntExpr_AMode_wrk()
1990 && e->Iex.Binop.arg2->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U8) { in iselIntExpr_AMode_wrk()
1991 UInt shift = e->Iex.Binop.arg2->Iex.Binop.arg2->Iex.Const.con->Ico.U8; in iselIntExpr_AMode_wrk()
1993 HReg r1 = iselIntExpr_R(env, e->Iex.Binop.arg1); in iselIntExpr_AMode_wrk()
1994 HReg r2 = iselIntExpr_R(env, e->Iex.Binop.arg2->Iex.Binop.arg1 ); in iselIntExpr_AMode_wrk()
2001 && e->Iex.Binop.op == Iop_Add64 in iselIntExpr_AMode_wrk()
2002 && e->Iex.Binop.arg2->tag == Iex_Const in iselIntExpr_AMode_wrk()
2003 && e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U64 in iselIntExpr_AMode_wrk()
2004 && fitsIn32Bits(e->Iex.Binop.arg2->Iex.Const.con->Ico.U64)) { in iselIntExpr_AMode_wrk()
2005 HReg r1 = iselIntExpr_R(env, e->Iex.Binop.arg1); in iselIntExpr_AMode_wrk()
2007 toUInt(e->Iex.Binop.arg2->Iex.Const.con->Ico.U64), in iselIntExpr_AMode_wrk()
2054 switch (e->Iex.Const.con->tag) { in iselIntExpr_RMI_wrk()
2056 if (fitsIn32Bits(e->Iex.Const.con->Ico.U64)) { in iselIntExpr_RMI_wrk()
2057 return AMD64RMI_Imm(toUInt(e->Iex.Const.con->Ico.U64)); in iselIntExpr_RMI_wrk()
2061 return AMD64RMI_Imm(e->Iex.Const.con->Ico.U32); break; in iselIntExpr_RMI_wrk()
2063 return AMD64RMI_Imm(0xFFFF & e->Iex.Const.con->Ico.U16); break; in iselIntExpr_RMI_wrk()
2065 return AMD64RMI_Imm(0xFF & e->Iex.Const.con->Ico.U8); break; in iselIntExpr_RMI_wrk()
2073 return AMD64RMI_Mem(AMD64AMode_IR(e->Iex.Get.offset, in iselIntExpr_RMI_wrk()
2079 && e->Iex.Load.end == Iend_LE) { in iselIntExpr_RMI_wrk()
2080 AMD64AMode* am = iselIntExpr_AMode(env, e->Iex.Load.addr); in iselIntExpr_RMI_wrk()
2123 switch (e->Iex.Const.con->tag) { in iselIntExpr_RI_wrk()
2125 if (fitsIn32Bits(e->Iex.Const.con->Ico.U64)) { in iselIntExpr_RI_wrk()
2126 return AMD64RI_Imm(toUInt(e->Iex.Const.con->Ico.U64)); in iselIntExpr_RI_wrk()
2130 return AMD64RI_Imm(e->Iex.Const.con->Ico.U32); in iselIntExpr_RI_wrk()
2132 return AMD64RI_Imm(0xFFFF & e->Iex.Const.con->Ico.U16); in iselIntExpr_RI_wrk()
2134 return AMD64RI_Imm(0xFF & e->Iex.Const.con->Ico.U8); in iselIntExpr_RI_wrk()
2179 return AMD64RM_Mem(AMD64AMode_IR(e->Iex.Get.offset, in iselIntExpr_RM_wrk()
2215 HReg r64 = lookupIRTemp(env, e->Iex.RdTmp.tmp); in iselCondCode_wrk()
2225 vassert(e->Iex.Const.con->tag == Ico_U1); in iselCondCode_wrk()
2226 vassert(e->Iex.Const.con->Ico.U1 == True in iselCondCode_wrk()
2227 || e->Iex.Const.con->Ico.U1 == False); in iselCondCode_wrk()
2231 return e->Iex.Const.con->Ico.U1 ? Acc_Z : Acc_NZ; in iselCondCode_wrk()
2235 if (e->tag == Iex_Unop && e->Iex.Unop.op == Iop_Not1) { in iselCondCode_wrk()
2237 return 1 ^ iselCondCode(env, e->Iex.Unop.arg); in iselCondCode_wrk()
2243 if (e->tag == Iex_Unop && e->Iex.Unop.op == Iop_64to1) { in iselCondCode_wrk()
2244 HReg reg = iselIntExpr_R(env, e->Iex.Unop.arg); in iselCondCode_wrk()
2252 if (e->tag == Iex_Unop && e->Iex.Unop.op == Iop_32to1) { in iselCondCode_wrk()
2253 HReg reg = iselIntExpr_R(env, e->Iex.Unop.arg); in iselCondCode_wrk()
2262 && e->Iex.Unop.op == Iop_CmpNEZ8) { in iselCondCode_wrk()
2263 HReg r = iselIntExpr_R(env, e->Iex.Unop.arg); in iselCondCode_wrk()
2272 && e->Iex.Unop.op == Iop_CmpNEZ16) { in iselCondCode_wrk()
2273 HReg r = iselIntExpr_R(env, e->Iex.Unop.arg); in iselCondCode_wrk()
2282 && e->Iex.Unop.op == Iop_CmpNEZ32) { in iselCondCode_wrk()
2283 HReg r1 = iselIntExpr_R(env, e->Iex.Unop.arg); in iselCondCode_wrk()
2308 && e->Iex.Unop.op == Iop_CmpNEZ64) { in iselCondCode_wrk()
2309 HReg r1 = iselIntExpr_R(env, e->Iex.Unop.arg); in iselCondCode_wrk()
2319 && (e->Iex.Binop.op == Iop_CmpEQ8 in iselCondCode_wrk()
2320 || e->Iex.Binop.op == Iop_CmpNE8 in iselCondCode_wrk()
2321 || e->Iex.Binop.op == Iop_CasCmpEQ8 in iselCondCode_wrk()
2322 || e->Iex.Binop.op == Iop_CasCmpNE8)) { in iselCondCode_wrk()
2323 if (isZeroU8(e->Iex.Binop.arg2)) { in iselCondCode_wrk()
2324 HReg r1 = iselIntExpr_R(env, e->Iex.Binop.arg1); in iselCondCode_wrk()
2326 switch (e->Iex.Binop.op) { in iselCondCode_wrk()
2332 HReg r1 = iselIntExpr_R(env, e->Iex.Binop.arg1); in iselCondCode_wrk()
2333 AMD64RMI* rmi2 = iselIntExpr_RMI(env, e->Iex.Binop.arg2); in iselCondCode_wrk()
2338 switch (e->Iex.Binop.op) { in iselCondCode_wrk()
2348 && (e->Iex.Binop.op == Iop_CmpEQ16 in iselCondCode_wrk()
2349 || e->Iex.Binop.op == Iop_CmpNE16 in iselCondCode_wrk()
2350 || e->Iex.Binop.op == Iop_CasCmpEQ16 in iselCondCode_wrk()
2351 || e->Iex.Binop.op == Iop_CasCmpNE16)) { in iselCondCode_wrk()
2352 HReg r1 = iselIntExpr_R(env, e->Iex.Binop.arg1); in iselCondCode_wrk()
2353 AMD64RMI* rmi2 = iselIntExpr_RMI(env, e->Iex.Binop.arg2); in iselCondCode_wrk()
2358 switch (e->Iex.Binop.op) { in iselCondCode_wrk()
2368 && e->Iex.Binop.op == Iop_CmpNE64 in iselCondCode_wrk()
2369 && e->Iex.Binop.arg1->tag == Iex_CCall in iselCondCode_wrk()
2370 && e->Iex.Binop.arg2->tag == Iex_Const) { in iselCondCode_wrk()
2371 IRExpr* cal = e->Iex.Binop.arg1; in iselCondCode_wrk()
2372 IRExpr* con = e->Iex.Binop.arg2; in iselCondCode_wrk()
2375 vassert(cal->Iex.CCall.retty == Ity_I64); /* else ill-typed IR */ in iselCondCode_wrk()
2376 vassert(con->Iex.Const.con->tag == Ico_U64); in iselCondCode_wrk()
2381 cal->Iex.CCall.cee, in iselCondCode_wrk()
2382 cal->Iex.CCall.retty, cal->Iex.CCall.args ); in iselCondCode_wrk()
2387 addInstr(env, AMD64Instr_Imm64(con->Iex.Const.con->Ico.U64, tmp)); in iselCondCode_wrk()
2395 && (e->Iex.Binop.op == Iop_CmpEQ64 in iselCondCode_wrk()
2396 || e->Iex.Binop.op == Iop_CmpNE64 in iselCondCode_wrk()
2397 || e->Iex.Binop.op == Iop_CmpLT64S in iselCondCode_wrk()
2398 || e->Iex.Binop.op == Iop_CmpLT64U in iselCondCode_wrk()
2399 || e->Iex.Binop.op == Iop_CmpLE64S in iselCondCode_wrk()
2400 || e->Iex.Binop.op == Iop_CmpLE64U in iselCondCode_wrk()
2401 || e->Iex.Binop.op == Iop_CasCmpEQ64 in iselCondCode_wrk()
2402 || e->Iex.Binop.op == Iop_CasCmpNE64 in iselCondCode_wrk()
2403 || e->Iex.Binop.op == Iop_ExpCmpNE64)) { in iselCondCode_wrk()
2404 HReg r1 = iselIntExpr_R(env, e->Iex.Binop.arg1); in iselCondCode_wrk()
2405 AMD64RMI* rmi2 = iselIntExpr_RMI(env, e->Iex.Binop.arg2); in iselCondCode_wrk()
2407 switch (e->Iex.Binop.op) { in iselCondCode_wrk()
2421 && (e->Iex.Binop.op == Iop_CmpEQ32 in iselCondCode_wrk()
2422 || e->Iex.Binop.op == Iop_CmpNE32 in iselCondCode_wrk()
2423 || e->Iex.Binop.op == Iop_CmpLT32S in iselCondCode_wrk()
2424 || e->Iex.Binop.op == Iop_CmpLT32U in iselCondCode_wrk()
2425 || e->Iex.Binop.op == Iop_CmpLE32S in iselCondCode_wrk()
2426 || e->Iex.Binop.op == Iop_CmpLE32U in iselCondCode_wrk()
2427 || e->Iex.Binop.op == Iop_CasCmpEQ32 in iselCondCode_wrk()
2428 || e->Iex.Binop.op == Iop_CasCmpNE32 in iselCondCode_wrk()
2429 || e->Iex.Binop.op == Iop_ExpCmpNE32)) { in iselCondCode_wrk()
2430 HReg r1 = iselIntExpr_R(env, e->Iex.Binop.arg1); in iselCondCode_wrk()
2431 AMD64RMI* rmi2 = iselIntExpr_RMI(env, e->Iex.Binop.arg2); in iselCondCode_wrk()
2433 switch (e->Iex.Binop.op) { in iselCondCode_wrk()
2481 lookupIRTempPair( rHi, rLo, env, e->Iex.RdTmp.tmp); in iselInt128Expr_wrk()
2487 switch (e->Iex.Binop.op) { in iselInt128Expr_wrk()
2496 Bool syned = toBool(e->Iex.Binop.op == Iop_MullS64); in iselInt128Expr_wrk()
2497 AMD64RM* rmLeft = iselIntExpr_RM(env, e->Iex.Binop.arg1); in iselInt128Expr_wrk()
2498 HReg rRight = iselIntExpr_R(env, e->Iex.Binop.arg2); in iselInt128Expr_wrk()
2517 Bool syned = toBool(e->Iex.Binop.op == Iop_DivModS128to64); in iselInt128Expr_wrk()
2518 AMD64RM* rmRight = iselIntExpr_RM(env, e->Iex.Binop.arg2); in iselInt128Expr_wrk()
2519 iselInt128Expr(&sHi,&sLo, env, e->Iex.Binop.arg1); in iselInt128Expr_wrk()
2532 *rHi = iselIntExpr_R(env, e->Iex.Binop.arg1); in iselInt128Expr_wrk()
2533 *rLo = iselIntExpr_R(env, e->Iex.Binop.arg2); in iselInt128Expr_wrk()
2571 return lookupIRTemp(env, e->Iex.RdTmp.tmp); in iselFltExpr_wrk()
2574 if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { in iselFltExpr_wrk()
2577 vassert(e->Iex.Load.ty == Ity_F32); in iselFltExpr_wrk()
2578 am = iselIntExpr_AMode(env, e->Iex.Load.addr); in iselFltExpr_wrk()
2584 && e->Iex.Binop.op == Iop_F64toF32) { in iselFltExpr_wrk()
2589 HReg src = iselDblExpr(env, e->Iex.Binop.arg2); in iselFltExpr_wrk()
2590 set_SSE_rounding_mode( env, e->Iex.Binop.arg1 ); in iselFltExpr_wrk()
2597 AMD64AMode* am = AMD64AMode_IR( e->Iex.Get.offset, in iselFltExpr_wrk()
2605 && e->Iex.Unop.op == Iop_ReinterpI32asF32) { in iselFltExpr_wrk()
2609 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); in iselFltExpr_wrk()
2616 if (e->tag == Iex_Binop && e->Iex.Binop.op == Iop_RoundF32toInt) { in iselFltExpr_wrk()
2618 HReg arg = iselFltExpr(env, e->Iex.Binop.arg2); in iselFltExpr_wrk()
2625 set_FPU_rounding_mode( env, e->Iex.Binop.arg1 ); in iselFltExpr_wrk()
2640 if (e->tag == Iex_Unop && e->Iex.Unop.op == Iop_NegF32) { in iselFltExpr_wrk()
2647 HReg src = iselFltExpr(env, e->Iex.Unop.arg); in iselFltExpr_wrk()
2659 if (e->tag == Iex_Qop && e->Iex.Qop.details->op == Iop_MAddF32) { in iselFltExpr_wrk()
2660 IRQop *qop = e->Iex.Qop.details; in iselFltExpr_wrk()
2759 return lookupIRTemp(env, e->Iex.RdTmp.tmp); in iselDblExpr_wrk()
2770 if (e->Iex.Const.con->tag == Ico_F64) { in iselDblExpr_wrk()
2771 u.f64 = e->Iex.Const.con->Ico.F64; in iselDblExpr_wrk()
2773 else if (e->Iex.Const.con->tag == Ico_F64i) { in iselDblExpr_wrk()
2774 u.u64 = e->Iex.Const.con->Ico.F64i; in iselDblExpr_wrk()
2789 if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { in iselDblExpr_wrk()
2792 vassert(e->Iex.Load.ty == Ity_F64); in iselDblExpr_wrk()
2793 am = iselIntExpr_AMode(env, e->Iex.Load.addr); in iselDblExpr_wrk()
2799 AMD64AMode* am = AMD64AMode_IR( e->Iex.Get.offset, in iselDblExpr_wrk()
2809 env, e->Iex.GetI.descr, in iselDblExpr_wrk()
2810 e->Iex.GetI.ix, e->Iex.GetI.bias ); in iselDblExpr_wrk()
2817 IRTriop *triop = e->Iex.Triop.details; in iselDblExpr_wrk()
2838 if (e->tag == Iex_Qop && e->Iex.Qop.details->op == Iop_MAddF64) { in iselDblExpr_wrk()
2839 IRQop *qop = e->Iex.Qop.details; in iselDblExpr_wrk()
2886 if (e->tag == Iex_Binop && e->Iex.Binop.op == Iop_RoundF64toInt) { in iselDblExpr_wrk()
2888 HReg arg = iselDblExpr(env, e->Iex.Binop.arg2); in iselDblExpr_wrk()
2895 set_FPU_rounding_mode( env, e->Iex.Binop.arg1 ); in iselDblExpr_wrk()
2910 IRTriop *triop = e->Iex.Triop.details; in iselDblExpr_wrk()
2970 if (e->tag == Iex_Binop && e->Iex.Binop.op == Iop_I64StoF64) { in iselDblExpr_wrk()
2972 HReg src = iselIntExpr_R(env, e->Iex.Binop.arg2); in iselDblExpr_wrk()
2973 set_SSE_rounding_mode( env, e->Iex.Binop.arg1 ); in iselDblExpr_wrk()
2979 if (e->tag == Iex_Unop && e->Iex.Unop.op == Iop_I32StoF64) { in iselDblExpr_wrk()
2981 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); in iselDblExpr_wrk()
2988 && (e->Iex.Unop.op == Iop_NegF64 in iselDblExpr_wrk()
2989 || e->Iex.Unop.op == Iop_AbsF64)) { in iselDblExpr_wrk()
2996 HReg src = iselDblExpr(env, e->Iex.Unop.arg); in iselDblExpr_wrk()
3004 if (e->Iex.Unop.op == Iop_NegF64) in iselDblExpr_wrk()
3015 switch (e->Iex.Binop.op) { in iselDblExpr_wrk()
3025 HReg arg = iselDblExpr(env, e->Iex.Binop.arg2); in iselDblExpr_wrk()
3027 Int nNeeded = e->Iex.Binop.op==Iop_TanF64 ? 2 : 1; in iselDblExpr_wrk()
3046 switch (e->Iex.Unop.op) { in iselDblExpr_wrk()
3063 AMD64RI* src = iselIntExpr_RI(env, e->Iex.Unop.arg); in iselDblExpr_wrk()
3075 f32 = iselFltExpr(env, e->Iex.Unop.arg); in iselDblExpr_wrk()
3088 vassert(typeOfIRExpr(env->type_env,e->Iex.ITE.cond) == Ity_I1); in iselDblExpr_wrk()
3089 r1 = iselDblExpr(env, e->Iex.ITE.iftrue); in iselDblExpr_wrk()
3090 r0 = iselDblExpr(env, e->Iex.ITE.iffalse); in iselDblExpr_wrk()
3093 AMD64CondCode cc = iselCondCode(env, e->Iex.ITE.cond); in iselDblExpr_wrk()
3130 return lookupIRTemp(env, e->Iex.RdTmp.tmp); in iselVecExpr_wrk()
3139 AMD64AMode_IR(e->Iex.Get.offset, hregAMD64_RBP()) in iselVecExpr_wrk()
3145 if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { in iselVecExpr_wrk()
3147 AMD64AMode* am = iselIntExpr_AMode(env, e->Iex.Load.addr); in iselVecExpr_wrk()
3154 vassert(e->Iex.Const.con->tag == Ico_V128); in iselVecExpr_wrk()
3155 switch (e->Iex.Const.con->Ico.V128) { in iselVecExpr_wrk()
3166 (e->Iex.Const.con->Ico.V128 >> 8) & 0xFF in iselVecExpr_wrk()
3169 (e->Iex.Const.con->Ico.V128 >> 0) & 0xFF in iselVecExpr_wrk()
3180 switch (e->Iex.Unop.op) { in iselVecExpr_wrk()
3183 HReg arg = iselVecExpr(env, e->Iex.Unop.arg); in iselVecExpr_wrk()
3203 HReg arg = iselVecExpr(env, e->Iex.Unop.arg); in iselVecExpr_wrk()
3218 HReg arg = iselVecExpr(env, e->Iex.Unop.arg); in iselVecExpr_wrk()
3232 HReg arg = iselVecExpr(env, e->Iex.Unop.arg); in iselVecExpr_wrk()
3249 HReg arg = iselVecExpr(env, e->Iex.Unop.arg); in iselVecExpr_wrk()
3265 HReg arg = iselVecExpr(env, e->Iex.Unop.arg); in iselVecExpr_wrk()
3275 AMD64RI* ri = iselIntExpr_RI(env, e->Iex.Unop.arg); in iselVecExpr_wrk()
3284 AMD64RMI* rmi = iselIntExpr_RMI(env, e->Iex.Unop.arg); in iselVecExpr_wrk()
3294 iselDVecExpr(&vHi, &vLo, env, e->Iex.Unop.arg); in iselVecExpr_wrk()
3295 return (e->Iex.Unop.op == Iop_V256toV128_1) ? vHi : vLo; in iselVecExpr_wrk()
3304 switch (e->Iex.Binop.op) { in iselVecExpr_wrk()
3309 HReg arg = iselVecExpr(env, e->Iex.Binop.arg2); in iselVecExpr_wrk()
3313 addInstr(env, (e->Iex.Binop.op == Iop_Sqrt64Fx2 in iselVecExpr_wrk()
3322 HReg srcV = iselVecExpr(env, e->Iex.Binop.arg1); in iselVecExpr_wrk()
3323 HReg srcI = iselIntExpr_R(env, e->Iex.Binop.arg2); in iselVecExpr_wrk()
3334 HReg srcV = iselVecExpr(env, e->Iex.Binop.arg1); in iselVecExpr_wrk()
3335 HReg srcI = iselIntExpr_R(env, e->Iex.Binop.arg2); in iselVecExpr_wrk()
3347 AMD64RI* qHi = iselIntExpr_RI(env, e->Iex.Binop.arg1); in iselVecExpr_wrk()
3348 AMD64RI* qLo = iselIntExpr_RI(env, e->Iex.Binop.arg2); in iselVecExpr_wrk()
3365 HReg argL = iselVecExpr(env, e->Iex.Binop.arg1); in iselVecExpr_wrk()
3366 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2); in iselVecExpr_wrk()
3381 HReg argL = iselVecExpr(env, e->Iex.Binop.arg1); in iselVecExpr_wrk()
3382 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2); in iselVecExpr_wrk()
3400 HReg argL = iselVecExpr(env, e->Iex.Binop.arg1); in iselVecExpr_wrk()
3401 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2); in iselVecExpr_wrk()
3419 HReg argL = iselVecExpr(env, e->Iex.Binop.arg1); in iselVecExpr_wrk()
3420 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2); in iselVecExpr_wrk()
3487 HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1); in iselVecExpr_wrk()
3488 HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2); in iselVecExpr_wrk()
3509 HReg greg = iselVecExpr(env, e->Iex.Binop.arg1); in iselVecExpr_wrk()
3510 AMD64RMI* rmi = iselIntExpr_RMI(env, e->Iex.Binop.arg2); in iselVecExpr_wrk()
3561 HReg argL = iselVecExpr(env, e->Iex.Binop.arg1); in iselVecExpr_wrk()
3562 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2); in iselVecExpr_wrk()
3613 HReg argL = iselVecExpr(env, e->Iex.Binop.arg1); in iselVecExpr_wrk()
3614 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); in iselVecExpr_wrk()
3659 IRTriop *triop = e->Iex.Triop.details; in iselVecExpr_wrk()
3700 HReg r1 = iselVecExpr(env, e->Iex.ITE.iftrue); in iselVecExpr_wrk()
3701 HReg r0 = iselVecExpr(env, e->Iex.ITE.iffalse); in iselVecExpr_wrk()
3704 AMD64CondCode cc = iselCondCode(env, e->Iex.ITE.cond); in iselVecExpr_wrk()
3748 lookupIRTempPair( rHi, rLo, env, e->Iex.RdTmp.tmp); in iselDVecExpr_wrk()
3756 AMD64AMode* am0 = AMD64AMode_IR(e->Iex.Get.offset + 0, rbp); in iselDVecExpr_wrk()
3757 AMD64AMode* am16 = AMD64AMode_IR(e->Iex.Get.offset + 16, rbp); in iselDVecExpr_wrk()
3768 HReg rA = iselIntExpr_R(env, e->Iex.Load.addr); in iselDVecExpr_wrk()
3779 vassert(e->Iex.Const.con->tag == Ico_V256); in iselDVecExpr_wrk()
3780 switch (e->Iex.Const.con->Ico.V256) { in iselDVecExpr_wrk()
3795 switch (e->Iex.Unop.op) { in iselDVecExpr_wrk()
3799 iselDVecExpr(&argHi, &argLo, env, e->Iex.Unop.arg); in iselDVecExpr_wrk()
3811 iselDVecExpr(&argHi, &argLo, env, e->Iex.Unop.arg); in iselDVecExpr_wrk()
3825 iselDVecExpr(&argHi, &argLo, env, e->Iex.Unop.arg); in iselDVecExpr_wrk()
3841 iselDVecExpr(&argHi, &argLo, env, e->Iex.Unop.arg); in iselDVecExpr_wrk()
3866 iselDVecExpr(&argHi, &argLo, env, e->Iex.Unop.arg); in iselDVecExpr_wrk()
3888 switch (e->Iex.Binop.op) { in iselDVecExpr_wrk()
3895 iselDVecExpr(&argLhi, &argLlo, env, e->Iex.Binop.arg1); in iselDVecExpr_wrk()
3896 iselDVecExpr(&argRhi, &argRlo, env, e->Iex.Binop.arg2); in iselDVecExpr_wrk()
3913 iselDVecExpr(&argLhi, &argLlo, env, e->Iex.Binop.arg1); in iselDVecExpr_wrk()
3914 iselDVecExpr(&argRhi, &argRlo, env, e->Iex.Binop.arg2); in iselDVecExpr_wrk()
3963 iselDVecExpr(&argLhi, &argLlo, env, e->Iex.Binop.arg1); in iselDVecExpr_wrk()
3964 iselDVecExpr(&argRhi, &argRlo, env, e->Iex.Binop.arg2); in iselDVecExpr_wrk()
3986 iselDVecExpr(&gregHi, &gregLo, env, e->Iex.Binop.arg1); in iselDVecExpr_wrk()
3987 AMD64RMI* rmi = iselIntExpr_RMI(env, e->Iex.Binop.arg2); in iselDVecExpr_wrk()
4006 *rHi = iselVecExpr(env, e->Iex.Binop.arg1); in iselDVecExpr_wrk()
4007 *rLo = iselVecExpr(env, e->Iex.Binop.arg2); in iselDVecExpr_wrk()
4040 iselDVecExpr(&argLhi, &argLlo, env, e->Iex.Binop.arg1); in iselDVecExpr_wrk()
4041 iselDVecExpr(&argRhi, &argRlo, env, e->Iex.Binop.arg2); in iselDVecExpr_wrk()
4118 iselDVecExpr(&argLhi, &argLlo, env, e->Iex.Binop.arg1); in iselDVecExpr_wrk()
4119 iselDVecExpr(&argRhi, &argRlo, env, e->Iex.Binop.arg2); in iselDVecExpr_wrk()
4177 IRTriop *triop = e->Iex.Triop.details; in iselDVecExpr_wrk()
4230 if (e->tag == Iex_Qop && e->Iex.Qop.details->op == Iop_64x4toV256) { in iselDVecExpr_wrk()
4238 AMD64RI* q3 = iselIntExpr_RI(env, e->Iex.Qop.details->arg1); in iselDVecExpr_wrk()
4239 AMD64RI* q2 = iselIntExpr_RI(env, e->Iex.Qop.details->arg2); in iselDVecExpr_wrk()
4240 AMD64RI* q1 = iselIntExpr_RI(env, e->Iex.Qop.details->arg3); in iselDVecExpr_wrk()
4241 AMD64RI* q0 = iselIntExpr_RI(env, e->Iex.Qop.details->arg4); in iselDVecExpr_wrk()
4257 iselDVecExpr(&r1Hi, &r1Lo, env, e->Iex.ITE.iftrue); in iselDVecExpr_wrk()
4258 iselDVecExpr(&r0Hi, &r0Lo, env, e->Iex.ITE.iffalse); in iselDVecExpr_wrk()
4263 AMD64CondCode cc = iselCondCode(env, e->Iex.ITE.cond); in iselDVecExpr_wrk()
4518 && stmt->Ist.WrTmp.data->Iex.Binop.op == Iop_Add64) { in iselStmt()
4841 IRConst* cdst = next->Iex.Const.con; in iselNext()