Lines Matching refs:vassert
154 vassert(r >= 0 && r < 16); in ppHRegARM()
159 vassert(r >= 0 && r < 32); in ppHRegARM()
164 vassert(r >= 0 && r < 32); in ppHRegARM()
169 vassert(r >= 0 && r < 16); in ppHRegARM()
210 vassert(-4095 <= simm13 && simm13 <= 4095); in ARMAMode1_RI()
219 vassert(0 <= shift && shift <= 3); in ARMAMode1_RRS()
238 vassert(0); in ppARMAMode1()
278 vassert(-255 <= simm9 && simm9 <= 255); in ARMAMode2_RI()
304 vassert(0); in ppARMAMode2()
341 vassert(simm11 >= -1020 && simm11 <= 1020); in mkARMAModeV()
342 vassert(0 == (simm11 & 3)); in mkARMAModeV()
416 vassert(sh >= 0 && sh < 32); in ROR32()
428 vassert(imm8 >= 0 && imm8 <= 255); in ARMRI84_I84()
429 vassert(imm4 >= 0 && imm4 <= 15); in ARMRI84_I84()
449 vassert(0); in ppARMRI84()
484 vassert(imm5 > 0 && imm5 <= 31); // zero is not allowed in ARMRI5_I5()
503 vassert(0); in ppARMRI5()
1144 vassert(cc != ARMcc_NV); in ARMInstr_LdSt32()
1157 vassert(cc != ARMcc_NV); in ARMInstr_LdSt16()
1168 vassert(cc != ARMcc_NV); in ARMInstr_LdSt8U()
1177 vassert(cc != ARMcc_NV); in ARMInstr_Ld8S()
1215 vassert(cond != ARMcc_AL); in ARMInstr_CMov()
1226 vassert(is_sane_RetLoc(rloc)); in ARMInstr_Call()
1239 vassert(szB == 8 || szB == 4 || szB == 2 || szB == 1); in ARMInstr_LdrEX()
1246 vassert(szB == 8 || szB == 4 || szB == 2 || szB == 1); in ARMInstr_StrEX()
1312 vassert(cond != ARMcc_AL); in ARMInstr_VCMovD()
1321 vassert(cond != ARMcc_AL); in ARMInstr_VCMovS()
1489 vassert(cond != ARMcc_AL); in ARMInstr_NCMovQ()
1514 vassert(amt >= 1 && amt <= 63); in ARMInstr_NShl64()
1530 vassert(i == 16); in fitsIn8x4()
1737 default: vassert(0); in ppARMInstr()
1748 default: vassert(0); in ppARMInstr()
2081 vassert(mode64 == False); in getRegUsage_ARMInstr()
2407 vassert(mode64 == False); in mapRegs_ARMInstr()
2669 vassert(offsetB >= 0); in genSpill_ARM()
2670 vassert(!hregIsVirtual(rreg)); in genSpill_ARM()
2671 vassert(mode64 == False); in genSpill_ARM()
2676 vassert(offsetB <= 4095); in genSpill_ARM()
2686 vassert(0 == (offsetB & 3)); in genSpill_ARM()
2695 vassert(offsetB <= 1020); in genSpill_ARM()
2724 vassert(offsetB >= 0); in genReload_ARM()
2725 vassert(!hregIsVirtual(rreg)); in genReload_ARM()
2726 vassert(mode64 == False); in genReload_ARM()
2731 vassert(offsetB <= 4095); in genReload_ARM()
2741 vassert(0 == (offsetB & 3)); in genReload_ARM()
2750 vassert(offsetB <= 1020); in genReload_ARM()
2783 vassert(hregClass(r) == HRcInt32); in iregEnc()
2784 vassert(!hregIsVirtual(r)); in iregEnc()
2786 vassert(n <= 15); in iregEnc()
2793 vassert(hregClass(r) == HRcFlt64); in dregEnc()
2794 vassert(!hregIsVirtual(r)); in dregEnc()
2796 vassert(n <= 31); in dregEnc()
2803 vassert(hregClass(r) == HRcFlt32); in fregEnc()
2804 vassert(!hregIsVirtual(r)); in fregEnc()
2806 vassert(n <= 31); in fregEnc()
2813 vassert(hregClass(r) == HRcVec128); in qregEnc()
2814 vassert(!hregIsVirtual(r)); in qregEnc()
2816 vassert(n <= 15); in qregEnc()
2881 vassert(0 == (ri->ARMri84.I84.imm4 & ~0x0F)); in skeletal_RI84()
2882 vassert(0 == (ri->ARMri84.I84.imm8 & ~0xFF)); in skeletal_RI84()
2900 vassert(imm5 >= 1 && imm5 <= 31); in skeletal_RI5()
2916 vassert(rD >= 0 && rD <= 14); // r15 not good to mess with! in imm32_to_ireg()
3011 vassert(0); /* lose */ in imm32_to_ireg_EXACTLY2()
3033 vassert(0); /* lose */ in is_imm32_to_ireg_EXACTLY2()
3041 vassert(rD <= 12); in do_load_or_store32()
3042 vassert(am->tag == ARMam1_RI); // RR case is not handled in do_load_or_store32()
3054 vassert(simm12 >= 0 && simm12 <= 4095); in do_load_or_store32()
3079 vassert(nbuf >= 32); in emit_ARMInstr()
3080 vassert(mode64 == False); in emit_ARMInstr()
3081 vassert(0 == (((HWord)buf) & 3)); in emit_ARMInstr()
3200 vassert(cc != ARMcc_NV); in emit_ARMInstr()
3211 vassert(simm12 >= 0 && simm12 <= 4095); in emit_ARMInstr()
3229 vassert(cc != ARMcc_NV); in emit_ARMInstr()
3241 vassert(simm8 >= 0 && simm8 <= 255); in emit_ARMInstr()
3244 vassert(!(bL == 0 && bS == 1)); // "! signed store" in emit_ARMInstr()
3266 else vassert(0); // ill-constructed insn in emit_ARMInstr()
3276 vassert(cc != ARMcc_NV); in emit_ARMInstr()
3288 vassert(simm8 >= 0 && simm8 <= 255); in emit_ARMInstr()
3308 vassert(disp_cp_chain_me_to_slowEP != NULL); in emit_ARMInstr()
3309 vassert(disp_cp_chain_me_to_fastEP != NULL); in emit_ARMInstr()
3318 vassert(i->ARMin.XDirect.cond != ARMcc_NV); in emit_ARMInstr()
3350 vassert(delta > 0 && delta < 40); in emit_ARMInstr()
3351 vassert((delta & 3) == 0); in emit_ARMInstr()
3353 vassert(notCond <= 13); /* Neither AL nor NV */ in emit_ARMInstr()
3367 vassert(disp_cp_xindir != NULL); in emit_ARMInstr()
3376 vassert(i->ARMin.XIndir.cond != ARMcc_NV); in emit_ARMInstr()
3396 vassert(delta > 0 && delta < 40); in emit_ARMInstr()
3397 vassert((delta & 3) == 0); in emit_ARMInstr()
3399 vassert(notCond <= 13); /* Neither AL nor NV */ in emit_ARMInstr()
3414 vassert(i->ARMin.XAssisted.cond != ARMcc_NV); in emit_ARMInstr()
3448 vassert(trcval != 0); in emit_ARMInstr()
3460 vassert(delta > 0 && delta < 40); in emit_ARMInstr()
3461 vassert((delta & 3) == 0); in emit_ARMInstr()
3463 vassert(notCond <= 13); /* Neither AL nor NV */ in emit_ARMInstr()
3492 default: vassert(0); in emit_ARMInstr()
3556 vassert(0); //ATC in emit_ARMInstr()
3562 vassert(0); in emit_ARMInstr()
3583 default: vassert(0); in emit_ARMInstr()
3625 vassert(0 == (off8 & 3)); in emit_ARMInstr()
3627 vassert(0 == (off8 & 0xFFFFFF00)); in emit_ARMInstr()
3642 vassert(0 == (off8 & 3)); in emit_ARMInstr()
3644 vassert(0 == (off8 & 0xFFFFFF00)); in emit_ARMInstr()
3662 vassert(pqrs != X1111); in emit_ARMInstr()
3687 vassert(pqrs != X1111); in emit_ARMInstr()
3764 vassert(cc < 16 && cc != ARMcc_AL); in emit_ARMInstr()
3773 vassert(cc < 16 && cc != ARMcc_AL); in emit_ARMInstr()
3819 vassert(qDhi != dHi && qDhi != dLo); in emit_ARMInstr()
3820 vassert(qDlo != dHi && qDlo != dLo); in emit_ARMInstr()
3914 vassert(0); in emit_ARMInstr()
3934 vassert(D <= 1 && Vd <= 15 && M <= 1 && Vm <= 15); in emit_ARMInstr()
3963 vassert(D <= 1 && Vd <= 15 && M <= 1 && Vm <= 15 && N <= 1 in emit_ARMInstr()
4004 vassert(hregClass(i->ARMin.NLdStQ.dQ) == HRcVec128); in emit_ARMInstr()
4024 vassert(hregClass(i->ARMin.NLdStD.dD) == HRcFlt64); in emit_ARMInstr()
4284 vassert(sz1 + sz2 < 2); in emit_ARMInstr()
4720 vassert(amt >= 1 && amt <= 63); in emit_ARMInstr()
4721 vassert(hregClass(regDreg) == HRcFlt64); in emit_ARMInstr()
4722 vassert(hregClass(regMreg) == HRcFlt64); in emit_ARMInstr()
4792 vassert(cc < 16 && cc != ARMcc_AL && cc != ARMcc_NV); in emit_ARMInstr()
4806 vassert(regD != regN); in emit_ARMInstr()
4838 vassert(evCheckSzB_ARM() == (UChar*)p - (UChar*)p0); in emit_ARMInstr()
4865 vassert(!(*is_profInc)); in emit_ARMInstr()
4881 vassert(((UChar*)p) - &buf[0] <= 32); in emit_ARMInstr()
4902 vassert(endness_host == VexEndnessLE); in chainXDirect_ARM()
4913 vassert(0 == (3 & (HWord)p)); in chainXDirect_ARM()
4914 vassert(is_imm32_to_ireg_EXACTLY2( in chainXDirect_ARM()
4916 vassert(p[2] == 0xE12FFF3C); in chainXDirect_ARM()
4947 vassert(0 == (delta & (Long)3)); in chainXDirect_ARM()
4966 vassert(uimm24 == simm24); in chainXDirect_ARM()
4988 vassert(endness_host == VexEndnessLE); in unchainXDirect_ARM()
5007 vassert(0 == (3 & (HWord)p)); in unchainXDirect_ARM()
5027 vassert(valid); in unchainXDirect_ARM()
5051 vassert(endness_host == VexEndnessLE); in patchProfInc_ARM()
5052 vassert(sizeof(ULong*) == 4); in patchProfInc_ARM()
5054 vassert(0 == (3 & (HWord)p)); in patchProfInc_ARM()
5055 vassert(is_imm32_to_ireg_EXACTLY2(p, /*r*/12, 0x65556555)); in patchProfInc_ARM()
5056 vassert(p[2] == 0xE59CB000); in patchProfInc_ARM()
5057 vassert(p[3] == 0xE29BB001); in patchProfInc_ARM()
5058 vassert(p[4] == 0xE58CB000); in patchProfInc_ARM()
5059 vassert(p[5] == 0xE59CB004); in patchProfInc_ARM()
5060 vassert(p[6] == 0xE2ABB000); in patchProfInc_ARM()
5061 vassert(p[7] == 0xE58CB004); in patchProfInc_ARM()