Lines Matching refs:r32

27 adcl eflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654333]
28 adcl eflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654334]
35 adcl eflags[0x1,0x0] : r32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
36 adcl eflags[0x1,0x1] : r32.ud[12345678] r32.ud[87654321] => 1.ud[100000000]
37 adcl eflags[0x1,0x0] : r32.ud[12345678] m32.ud[87654321] => 1.ud[99999999]
38 adcl eflags[0x1,0x1] : r32.ud[12345678] m32.ud[87654321] => 1.ud[100000000]
39 adcl eflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
40 adcl eflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[100000000]
68 addl imm8[12] r32.ud[87654321] => 1.ud[87654333]
72 addl r32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
73 addl r32.ud[12345678] m32.ud[87654321] => 1.ud[99999999]
74 addl m32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
95 andl imm8[0x31] r32.ud[0x12345678] => 1.ud[0x00000030]
99 andl r32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x02005430]
100 andl r32.ud[0x86427531] m32.ud[0x12345678] => 1.ud[0x02005430]
101 andl m32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x02005430]
114 bsfl r32.ud[0x13572468] r32.ud[0] => 1.ud[3]
115 bsfl m32.ud[0x75318642] r32.ud[0] => 1.ud[1]
120 bsrl r32.ud[0x13572468] r32.ud[0] => 1.ud[28]
121 bsrl m32.ud[0x75318642] r32.ud[0] => 1.ud[30]
124 bswapl r32.ud[0x12345678] => 0.ud[0x78563412]
134 btl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
135 btl imm8[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
138 btl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
139 btl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
140 btl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
141 btl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
158 btcl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
159 btcl imm8[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
162 btcl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
163 btcl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
164 btcl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
165 btcl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
182 btrl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
183 btrl imm8[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
186 btrl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
187 btrl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
188 btrl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
189 btrl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
206 btsl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
207 btsl imm8[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
210 btsl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
211 btsl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
212 btsl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
213 btsl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
374 cmpl imm8[3] r32.ud[2] => eflags[0x010,0x010]
375 cmpl imm8[2] r32.ud[3] => eflags[0x010,0x000]
376 cmpl imm8[12] r32.ud[12] => eflags[0x044,0x044]
377 ###cmpl imm8[12] r32.ud[34] => eflags[0x044,0x000]
378 cmpl imm8[34] r32.ud[12] => eflags[0x081,0x081]
379 cmpl imm8[12] r32.ud[34] => eflags[0x081,0x000]
380 cmpl imm8[100] r32.sd[-2147483600] => eflags[0x800,0x800]
381 cmpl imm8[50] r32.sd[-50] => eflags[0x800,0x000]
382 cmpl imm8[-50] r32.sd[50] => eflags[0x800,0x000]
383 cmpl imm8[-100] r32.sd[2147483600] => eflags[0x800,0x800]
404 cmpl imm32[3] r32.ud[2] => eflags[0x010,0x010]
405 cmpl imm32[2] r32.ud[3] => eflags[0x010,0x000]
406 cmpl imm32[12] r32.ud[12] => eflags[0x044,0x044]
407 cmpl imm32[12] r32.ud[34] => eflags[0x044,0x000]
408 cmpl imm32[34] r32.ud[12] => eflags[0x081,0x081]
409 cmpl imm32[12] r32.ud[34] => eflags[0x081,0x000]
410 cmpl imm32[100] r32.sd[-2147483600] => eflags[0x800,0x800]
411 cmpl imm32[50] r32.sd[-50] => eflags[0x800,0x000]
412 cmpl imm32[-50] r32.sd[50] => eflags[0x800,0x000]
413 cmpl imm32[-100] r32.sd[2147483600] => eflags[0x800,0x800]
424 cmpl r32.ud[3] r32.ud[2] => eflags[0x010,0x010]
425 cmpl r32.ud[2] r32.ud[3] => eflags[0x010,0x000]
426 cmpl r32.ud[12] r32.ud[12] => eflags[0x044,0x044]
427 cmpl r32.ud[12] r32.ud[34] => eflags[0x044,0x000]
428 cmpl r32.ud[34] r32.ud[12] => eflags[0x081,0x081]
429 cmpl r32.ud[12] r32.ud[34] => eflags[0x081,0x000]
430 cmpl r32.ud[100] r32.sd[-2147483600] => eflags[0x800,0x800]
431 cmpl r32.ud[50] r32.sd[-50] => eflags[0x800,0x000]
432 cmpl r32.sd[-50] r32.sd[50] => eflags[0x800,0x000]
433 cmpl r32.sd[-100] r32.sd[2147483600] => eflags[0x800,0x800]
434 cmpl r32.ud[3] m32.ud[2] => eflags[0x010,0x010]
435 cmpl r32.ud[2] m32.ud[3] => eflags[0x010,0x000]
436 cmpl r32.ud[12] m32.ud[12] => eflags[0x044,0x044]
437 cmpl r32.ud[12] m32.ud[34] => eflags[0x044,0x000]
438 cmpl r32.ud[34] m32.ud[12] => eflags[0x081,0x081]
439 cmpl r32.ud[12] m32.ud[34] => eflags[0x081,0x000]
440 cmpl r32.ud[100] m32.sd[-2147483600] => eflags[0x800,0x800]
441 cmpl r32.ud[50] m32.sd[-50] => eflags[0x800,0x000]
442 cmpl r32.sd[-50] m32.sd[50] => eflags[0x800,0x000]
443 cmpl r32.sd[-100] m32.sd[2147483600] => eflags[0x800,0x800]
444 cmpl m32.ud[3] r32.ud[2] => eflags[0x010,0x010]
445 cmpl m32.ud[2] r32.ud[3] => eflags[0x010,0x000]
446 cmpl m32.ud[12] r32.ud[12] => eflags[0x044,0x044]
447 cmpl m32.ud[12] r32.ud[34] => eflags[0x044,0x000]
448 cmpl m32.ud[34] r32.ud[12] => eflags[0x081,0x081]
449 cmpl m32.ud[12] r32.ud[34] => eflags[0x081,0x000]
450 cmpl m32.ud[100] r32.sd[-2147483600] => eflags[0x800,0x800]
451 cmpl m32.ud[50] r32.sd[-50] => eflags[0x800,0x000]
452 cmpl m32.sd[-50] r32.sd[50] => eflags[0x800,0x000]
453 ###cmpl m32.sd[-100] r32.sd[2147483600] => eflags[0x800,0x800]
542 ###cmpxchgl eflags[0x40,0x00] eax.ud[1234] : r32.ud[5678] r32.ud[1234] => eflags[0x40,0x40] eax.ud[…
543 ###cmpxchgl eflags[0x40,0x40] eax.ud[1234] : r32.ud[5678] r32.ud[3456] => eflags[0x40,0x00] eax.ud[…
544 cmpxchgl eflags[0x40,0x00] eax.ud[1234] : r32.ud[5678] m32.ud[1234] => eflags[0x40,0x40] eax.ud[123…
545 cmpxchgl eflags[0x40,0x40] eax.ud[1234] : r32.ud[5678] m32.ud[3456] => eflags[0x40,0x00] eax.ud[345…
560 decl r32.ud[12345678] => 0.ud[12345677]
568 divl edx.ud[251958] eax.ud[673192206] : r32.ud[87654321] => eax.ud[12345678] edx.ud[20783136]
576 idivl edx.sd[-251959] eax.sd[-673192206] : r32.sd[87654321] => eax.sd[-12345678] edx.sd[-20783136]
584 imull eax.sd[-12345678] : r32.sd[12345678] => edx.sd[-35488] eax.sd[-260846532]
596 imull imm8[123] r32.ud[67890] => 1.ud[8350470]
597 imull imm8[123] r32.ud[67890] r32.ud[0] => 2.ud[8350470]
598 imull imm8[123] m32.ud[67890] r32.ud[0] => 2.ud[8350470]
599 imull imm32[12345] r32.ud[67890] => 1.ud[838102050]
600 imull imm32[12345] r32.ud[67890] r32.ud[0] => 2.ud[838102050]
601 imull imm32[12345] m32.ud[67890] r32.ud[0] => 2.ud[838102050]
602 imull r32.ud[12345] r32.ud[67890] => 1.ud[838102050]
603 imull m32.ud[12345] r32.ud[67890] => 1.ud[838102050]
616 incl r32.ud[12345678] => 0.ud[12345679]
632 movl imm32[12345678] r32.ud[0] => 1.ud[12345678]
634 movl r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
635 movl r32.ud[12345678] m32.ud[0] => 1.ud[12345678]
636 movl m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
645 movsbl r8.sb[123] r32.sd[0] => 1.sd[123]
646 movsbl m8.sb[-123] r32.sd[0] => 1.sd[-123]
647 movswl r16.sw[12345] r32.sd[0] => 1.sd[12345]
648 movswl m16.sw[-12345] r32.sd[0] => 1.sd[-12345]
655 movzbl r8.ub[123] r32.ud[0] => 1.ud[123]
656 movzbl m8.ub[246] r32.ud[0] => 1.ud[246]
657 movzwl r16.uw[12345] r32.ud[0] => 1.ud[12345]
658 movzwl m16.uw[49380] r32.ud[0] => 1.ud[49380]
667 mull eax.ud[12345678] : r32.ud[12345678] => edx.ud[35487] eax.ud[260846532]
675 negl r32.sd[12345678] => 0.sd[-12345678]
683 notl r32.ud[0xff00f0ca] => 0.ud[0x00ff0f35]
700 orl imm8[0x31] r32.ud[0x12345678] => 1.ud[0x12345679]
704 orl r32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x96767779]
705 orl r32.ud[0x86427531] m32.ud[0x12345678] => 1.ud[0x96767779]
706 orl m32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x96767779]
729 ###rcll eflags[0x1,0x0] : r32.ud[0xff00f0ca] => 0.ud[0xfe01e194] eflags[0x1,0x1]
731 ###rcll eflags[0x1,0x0] : imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1]
733 ###rcll eflags[0x1,0x0] : cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1]
753 rcrl eflags[0x1,0x1] : r32.ud[0xff00f0ca] => 0.ud[0xff807865] eflags[0x1,0x0]
755 rcrl eflags[0x1,0x0] : imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1]
757 rcrl eflags[0x1,0x0] : cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1]
777 roll r32.ud[0xff00f0ca] => 0.ud[0xfe01e195]
779 roll imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0caff]
781 roll cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0caff]
801 rorl r32.ud[0xff00f0ca] => 0.ud[0x7f807865]
803 rorl imm8[8] r32.ud[0xff00f0ca] => 1.ud[0xcaff00f0]
805 rorl cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0xcaff00f0]
827 sall r32.ud[0xff00f0ca] => 0.ud[0xfe01e194]
829 sall imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca00]
831 sall cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca00]
851 sarl r32.ud[0xff00f0ca] => 0.ud[0xff807865]
853 sarl imm8[8] r32.ud[0xff00f0ca] => 1.ud[0xffff00f0]
855 sarl cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0xffff00f0]
889 sbbl eflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654309]
890 sbbl eflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654308]
897 sbbl eflags[0x1,0x0] : r32.ud[12345678] r32.ud[87654321] => 1.ud[75308643]
898 sbbl eflags[0x1,0x1] : r32.ud[12345678] r32.ud[87654321] => 1.ud[75308642]
899 ###sbbl eflags[0x1,0x0] : r32.ud[12345678] m32.ud[87654321] => 1.ud[75308643]
900 ###sbbl eflags[0x1,0x1] : r32.ud[12345678] m32.ud[87654321] => 1.ud[75308642]
901 sbbl eflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[75308643]
902 sbbl eflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[75308642]
1121 shll r32.ud[0xff00f0ca] => 0.ud[0xfe01e194]
1123 shll imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca00]
1125 shll cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca00]
1145 shrl r32.ud[0xff00f0ca] => 0.ud[0x7f807865]
1147 shrl imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00ff00f0]
1149 shrl cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00ff00f0]
1165 ###shldl imm8[1] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0xfe01e195]
1166 ###shldl imm8[1] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0xfe01e195]
1167 ###shldl imm8[8] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0x00f0caff]
1168 ###shldl imm8[8] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0x00f0caff]
1169 shldl cl.ub[1] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0xfe01e195]
1170 shldl cl.ub[1] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0xfe01e195]
1171 shldl cl.ub[8] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0x00f0caff]
1172 shldl cl.ub[8] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0x00f0caff]
1189 shrdl imm8[1] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0x7f807865]
1190 shrdl imm8[1] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0x7f807865]
1191 shrdl imm8[8] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0xcaff00f0]
1192 shrdl imm8[8] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0xcaff00f0]
1193 shrdl cl.ub[1] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0x7f807865]
1194 shrdl cl.ub[1] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0x7f807865]
1195 shrdl cl.ub[8] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0xcaff00f0]
1196 shrdl cl.ub[8] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0xcaff00f0]
1222 subl imm8[12] r32.ud[87654321] => 1.ud[87654309]
1223 subl imm32[12345678] r32.ud[87654321] => 1.ud[75308643]
1226 subl r32.ud[12345678] r32.ud[87654321] => 1.ud[75308643]
1227 subl r32.ud[12345678] m32.ud[87654321] => 1.ud[75308643]
1228 subl m32.ud[12345678] r32.ud[87654321] => 1.ud[75308643]
1301 testl r32.ud[0x1a1a1a1a] r32.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
1302 testl r32.ud[0x5a5a5a5a] r32.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
1303 testl r32.ud[0x1a1a1a1a] r32.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
1304 testl r32.ud[0xa1a1a1a1] r32.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
1305 testl r32.ud[0xa5a5a5a5] r32.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
1306 testl r32.ud[0x1a1a1a1a] m32.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
1307 testl r32.ud[0x5a5a5a5a] m32.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
1308 testl r32.ud[0x1a1a1a1a] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
1309 testl r32.ud[0xa1a1a1a1] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
1310 testl r32.ud[0xa5a5a5a5] m32.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
1340 ###xaddl r32.ud[12345678] r32.ud[87654321] => 0.ud[87654321] 1.ud[99999999]
1341 xaddl r32.ud[12345678] m32.ud[87654321] => 0.ud[87654321] 1.ud[99999999]
1355 xchgl r32.ud[12345678] m32.ud[87654321] => 0.ud[87654321] 1.ud[12345678]
1356 xchgl m32.ud[12345678] r32.ud[87654321] => 0.ud[87654321] 1.ud[12345678]
1375 xorl imm8[0x31] r32.ud[0x12345678] => 1.ud[0x12345649]
1379 xorl r32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x94762349]
1380 xorl r32.ud[0x86427531] m32.ud[0x12345678] => 1.ud[0x94762349]
1381 xorl m32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x94762349]