1 #ifndef _ARBEL_H
2 #define _ARBEL_H
3
4 /** @file
5 *
6 * Mellanox Arbel Infiniband HCA driver
7 *
8 */
9
10 FILE_LICENCE ( GPL2_OR_LATER );
11
12 #include <stdint.h>
13 #include <gpxe/uaccess.h>
14 #include "mlx_bitops.h"
15 #include "MT25218_PRM.h"
16
17 /*
18 * Hardware constants
19 *
20 */
21
22 /* Ports in existence */
23 #define ARBEL_NUM_PORTS 2
24 #define ARBEL_PORT_BASE 1
25
26 /* PCI BARs */
27 #define ARBEL_PCI_CONFIG_BAR PCI_BASE_ADDRESS_0
28 #define ARBEL_PCI_CONFIG_BAR_SIZE 0x100000
29 #define ARBEL_PCI_UAR_BAR PCI_BASE_ADDRESS_2
30 #define ARBEL_PCI_UAR_IDX 1
31 #define ARBEL_PCI_UAR_SIZE 0x1000
32
33 /* UAR context table (UCE) resource types */
34 #define ARBEL_UAR_RES_NONE 0x00
35 #define ARBEL_UAR_RES_CQ_CI 0x01
36 #define ARBEL_UAR_RES_CQ_ARM 0x02
37 #define ARBEL_UAR_RES_SQ 0x03
38 #define ARBEL_UAR_RES_RQ 0x04
39 #define ARBEL_UAR_RES_GROUP_SEP 0x07
40
41 /* Work queue entry and completion queue entry opcodes */
42 #define ARBEL_OPCODE_SEND 0x0a
43 #define ARBEL_OPCODE_RECV_ERROR 0xfe
44 #define ARBEL_OPCODE_SEND_ERROR 0xff
45
46 /* HCA command register opcodes */
47 #define ARBEL_HCR_QUERY_DEV_LIM 0x0003
48 #define ARBEL_HCR_QUERY_FW 0x0004
49 #define ARBEL_HCR_INIT_HCA 0x0007
50 #define ARBEL_HCR_CLOSE_HCA 0x0008
51 #define ARBEL_HCR_INIT_IB 0x0009
52 #define ARBEL_HCR_CLOSE_IB 0x000a
53 #define ARBEL_HCR_SW2HW_MPT 0x000d
54 #define ARBEL_HCR_MAP_EQ 0x0012
55 #define ARBEL_HCR_SW2HW_EQ 0x0013
56 #define ARBEL_HCR_HW2SW_EQ 0x0014
57 #define ARBEL_HCR_SW2HW_CQ 0x0016
58 #define ARBEL_HCR_HW2SW_CQ 0x0017
59 #define ARBEL_HCR_RST2INIT_QPEE 0x0019
60 #define ARBEL_HCR_INIT2RTR_QPEE 0x001a
61 #define ARBEL_HCR_RTR2RTS_QPEE 0x001b
62 #define ARBEL_HCR_RTS2RTS_QPEE 0x001c
63 #define ARBEL_HCR_2RST_QPEE 0x0021
64 #define ARBEL_HCR_MAD_IFC 0x0024
65 #define ARBEL_HCR_READ_MGM 0x0025
66 #define ARBEL_HCR_WRITE_MGM 0x0026
67 #define ARBEL_HCR_MGID_HASH 0x0027
68 #define ARBEL_HCR_RUN_FW 0x0ff6
69 #define ARBEL_HCR_DISABLE_LAM 0x0ff7
70 #define ARBEL_HCR_ENABLE_LAM 0x0ff8
71 #define ARBEL_HCR_UNMAP_ICM 0x0ff9
72 #define ARBEL_HCR_MAP_ICM 0x0ffa
73 #define ARBEL_HCR_UNMAP_ICM_AUX 0x0ffb
74 #define ARBEL_HCR_MAP_ICM_AUX 0x0ffc
75 #define ARBEL_HCR_SET_ICM_SIZE 0x0ffd
76 #define ARBEL_HCR_UNMAP_FA 0x0ffe
77 #define ARBEL_HCR_MAP_FA 0x0fff
78
79 /* Service types */
80 #define ARBEL_ST_UD 0x03
81
82 /* MTUs */
83 #define ARBEL_MTU_2048 0x04
84
85 #define ARBEL_NO_EQ 64
86
87 #define ARBEL_INVALID_LKEY 0x00000100UL
88
89 #define ARBEL_PAGE_SIZE 4096
90
91 #define ARBEL_DB_POST_SND_OFFSET 0x10
92 #define ARBEL_DB_EQ_OFFSET(_eqn) ( 0x08 * (_eqn) )
93
94 #define ARBEL_QPEE_OPT_PARAM_QKEY 0x00000020UL
95
96 #define ARBEL_MAP_EQ ( 0UL << 31 )
97 #define ARBEL_UNMAP_EQ ( 1UL << 31 )
98
99 #define ARBEL_EV_PORT_STATE_CHANGE 0x09
100
101 /*
102 * Datatypes that seem to be missing from the autogenerated documentation
103 *
104 */
105 struct arbelprm_mgm_hash_st {
106 pseudo_bit_t reserved0[0x00020];
107 /* -------------- */
108 pseudo_bit_t hash[0x00010];
109 pseudo_bit_t reserved1[0x00010];
110 } __attribute__ (( packed ));
111
112 struct arbelprm_scalar_parameter_st {
113 pseudo_bit_t reserved0[0x00020];
114 /* -------------- */
115 pseudo_bit_t value[0x00020];
116 } __attribute__ (( packed ));
117
118 struct arbelprm_event_mask_st {
119 pseudo_bit_t reserved0[0x00020];
120 /* -------------- */
121 pseudo_bit_t completion[0x00001];
122 pseudo_bit_t reserved1[0x0008];
123 pseudo_bit_t port_state_change[0x00001];
124 pseudo_bit_t reserved2[0x00016];
125 } __attribute__ (( packed ));
126
127 struct arbelprm_eq_set_ci_st {
128 pseudo_bit_t ci[0x00020];
129 } __attribute__ (( packed ));
130
131 struct arbelprm_port_state_change_event_st {
132 pseudo_bit_t reserved[0x00020];
133 struct arbelprm_port_state_change_st data;
134 } __attribute__ (( packed ));
135
136 /*
137 * Wrapper structures for hardware datatypes
138 *
139 */
140
141 struct MLX_DECLARE_STRUCT ( arbelprm_access_lam );
142 struct MLX_DECLARE_STRUCT ( arbelprm_completion_queue_context );
143 struct MLX_DECLARE_STRUCT ( arbelprm_completion_queue_entry );
144 struct MLX_DECLARE_STRUCT ( arbelprm_completion_with_error );
145 struct MLX_DECLARE_STRUCT ( arbelprm_cq_arm_db_record );
146 struct MLX_DECLARE_STRUCT ( arbelprm_cq_ci_db_record );
147 struct MLX_DECLARE_STRUCT ( arbelprm_event_mask );
148 struct MLX_DECLARE_STRUCT ( arbelprm_event_queue_entry );
149 struct MLX_DECLARE_STRUCT ( arbelprm_eq_set_ci );
150 struct MLX_DECLARE_STRUCT ( arbelprm_eqc );
151 struct MLX_DECLARE_STRUCT ( arbelprm_hca_command_register );
152 struct MLX_DECLARE_STRUCT ( arbelprm_init_hca );
153 struct MLX_DECLARE_STRUCT ( arbelprm_init_ib );
154 struct MLX_DECLARE_STRUCT ( arbelprm_mad_ifc );
155 struct MLX_DECLARE_STRUCT ( arbelprm_mgm_entry );
156 struct MLX_DECLARE_STRUCT ( arbelprm_mgm_hash );
157 struct MLX_DECLARE_STRUCT ( arbelprm_mpt );
158 struct MLX_DECLARE_STRUCT ( arbelprm_port_state_change_event );
159 struct MLX_DECLARE_STRUCT ( arbelprm_qp_db_record );
160 struct MLX_DECLARE_STRUCT ( arbelprm_qp_ee_state_transitions );
161 struct MLX_DECLARE_STRUCT ( arbelprm_query_dev_lim );
162 struct MLX_DECLARE_STRUCT ( arbelprm_query_fw );
163 struct MLX_DECLARE_STRUCT ( arbelprm_queue_pair_ee_context_entry );
164 struct MLX_DECLARE_STRUCT ( arbelprm_recv_wqe_segment_next );
165 struct MLX_DECLARE_STRUCT ( arbelprm_scalar_parameter );
166 struct MLX_DECLARE_STRUCT ( arbelprm_send_doorbell );
167 struct MLX_DECLARE_STRUCT ( arbelprm_ud_address_vector );
168 struct MLX_DECLARE_STRUCT ( arbelprm_virtual_physical_mapping );
169 struct MLX_DECLARE_STRUCT ( arbelprm_wqe_segment_ctrl_send );
170 struct MLX_DECLARE_STRUCT ( arbelprm_wqe_segment_data_ptr );
171 struct MLX_DECLARE_STRUCT ( arbelprm_wqe_segment_next );
172 struct MLX_DECLARE_STRUCT ( arbelprm_wqe_segment_ud );
173
174 /*
175 * Composite hardware datatypes
176 *
177 */
178
179 #define ARBEL_MAX_GATHER 1
180
181 struct arbelprm_ud_send_wqe {
182 struct arbelprm_wqe_segment_next next;
183 struct arbelprm_wqe_segment_ctrl_send ctrl;
184 struct arbelprm_wqe_segment_ud ud;
185 struct arbelprm_wqe_segment_data_ptr data[ARBEL_MAX_GATHER];
186 } __attribute__ (( packed ));
187
188 #define ARBEL_MAX_SCATTER 1
189
190 struct arbelprm_recv_wqe {
191 /* The autogenerated header is inconsistent between send and
192 * receive WQEs. The "ctrl" structure for receive WQEs is
193 * defined to include the "next" structure. Since the "ctrl"
194 * part of the "ctrl" structure contains only "reserved, must
195 * be zero" bits, we ignore its definition and provide
196 * something more usable.
197 */
198 struct arbelprm_recv_wqe_segment_next next;
199 uint32_t ctrl[2]; /* All "reserved, must be zero" */
200 struct arbelprm_wqe_segment_data_ptr data[ARBEL_MAX_SCATTER];
201 } __attribute__ (( packed ));
202
203 union arbelprm_completion_entry {
204 struct arbelprm_completion_queue_entry normal;
205 struct arbelprm_completion_with_error error;
206 } __attribute__ (( packed ));
207
208 union arbelprm_event_entry {
209 struct arbelprm_event_queue_entry generic;
210 struct arbelprm_port_state_change_event port_state_change;
211 } __attribute__ (( packed ));
212
213 union arbelprm_doorbell_record {
214 struct arbelprm_cq_arm_db_record cq_arm;
215 struct arbelprm_cq_ci_db_record cq_ci;
216 struct arbelprm_qp_db_record qp;
217 } __attribute__ (( packed ));
218
219 union arbelprm_doorbell_register {
220 struct arbelprm_send_doorbell send;
221 uint32_t dword[2];
222 } __attribute__ (( packed ));
223
224 union arbelprm_eq_doorbell_register {
225 struct arbelprm_eq_set_ci ci;
226 uint32_t dword[1];
227 } __attribute__ (( packed ));
228
229 union arbelprm_mad {
230 struct arbelprm_mad_ifc ifc;
231 union ib_mad mad;
232 } __attribute__ (( packed ));
233
234 /*
235 * gPXE-specific definitions
236 *
237 */
238
239 /** Arbel device limits */
240 struct arbel_dev_limits {
241 /** Number of reserved QPs */
242 unsigned int reserved_qps;
243 /** QP context entry size */
244 size_t qpc_entry_size;
245 /** Extended QP context entry size */
246 size_t eqpc_entry_size;
247 /** Number of reserved SRQs */
248 unsigned int reserved_srqs;
249 /** SRQ context entry size */
250 size_t srqc_entry_size;
251 /** Number of reserved EEs */
252 unsigned int reserved_ees;
253 /** EE context entry size */
254 size_t eec_entry_size;
255 /** Extended EE context entry size */
256 size_t eeec_entry_size;
257 /** Number of reserved CQs */
258 unsigned int reserved_cqs;
259 /** CQ context entry size */
260 size_t cqc_entry_size;
261 /** Number of reserved EQs */
262 unsigned int reserved_eqs;
263 /** Number of reserved MTTs */
264 unsigned int reserved_mtts;
265 /** MTT entry size */
266 size_t mtt_entry_size;
267 /** Number of reserved MRWs */
268 unsigned int reserved_mrws;
269 /** MPT entry size */
270 size_t mpt_entry_size;
271 /** Number of reserved RDBs */
272 unsigned int reserved_rdbs;
273 /** EQ context entry size */
274 size_t eqc_entry_size;
275 /** Number of reserved UARs */
276 unsigned int reserved_uars;
277 };
278
279 /** Alignment of Arbel send work queue entries */
280 #define ARBEL_SEND_WQE_ALIGN 128
281
282 /** An Arbel send work queue entry */
283 union arbel_send_wqe {
284 struct arbelprm_ud_send_wqe ud;
285 uint8_t force_align[ARBEL_SEND_WQE_ALIGN];
286 } __attribute__ (( packed ));
287
288 /** An Arbel send work queue */
289 struct arbel_send_work_queue {
290 /** Doorbell record number */
291 unsigned int doorbell_idx;
292 /** Work queue entries */
293 union arbel_send_wqe *wqe;
294 /** Size of work queue */
295 size_t wqe_size;
296 };
297
298 /** Alignment of Arbel receive work queue entries */
299 #define ARBEL_RECV_WQE_ALIGN 64
300
301 /** An Arbel receive work queue entry */
302 union arbel_recv_wqe {
303 struct arbelprm_recv_wqe recv;
304 uint8_t force_align[ARBEL_RECV_WQE_ALIGN];
305 } __attribute__ (( packed ));
306
307 /** An Arbel receive work queue */
308 struct arbel_recv_work_queue {
309 /** Doorbell record number */
310 unsigned int doorbell_idx;
311 /** Work queue entries */
312 union arbel_recv_wqe *wqe;
313 /** Size of work queue */
314 size_t wqe_size;
315 };
316
317 /** Maximum number of allocatable queue pairs
318 *
319 * This is a policy decision, not a device limit.
320 */
321 #define ARBEL_MAX_QPS 8
322
323 /** Base queue pair number */
324 #define ARBEL_QPN_BASE 0x550000
325
326 /** An Arbel queue pair */
327 struct arbel_queue_pair {
328 /** Send work queue */
329 struct arbel_send_work_queue send;
330 /** Receive work queue */
331 struct arbel_recv_work_queue recv;
332 };
333
334 /** Maximum number of allocatable completion queues
335 *
336 * This is a policy decision, not a device limit.
337 */
338 #define ARBEL_MAX_CQS 8
339
340 /** An Arbel completion queue */
341 struct arbel_completion_queue {
342 /** Consumer counter doorbell record number */
343 unsigned int ci_doorbell_idx;
344 /** Arm queue doorbell record number */
345 unsigned int arm_doorbell_idx;
346 /** Completion queue entries */
347 union arbelprm_completion_entry *cqe;
348 /** Size of completion queue */
349 size_t cqe_size;
350 };
351
352 /** Maximum number of allocatable event queues
353 *
354 * This is a policy decision, not a device limit.
355 */
356 #define ARBEL_MAX_EQS 64
357
358 /** A Arbel event queue */
359 struct arbel_event_queue {
360 /** Event queue entries */
361 union arbelprm_event_entry *eqe;
362 /** Size of event queue */
363 size_t eqe_size;
364 /** Event queue number */
365 unsigned long eqn;
366 /** Next event queue entry index */
367 unsigned long next_idx;
368 /** Doorbell register */
369 void *doorbell;
370 };
371
372 /** Number of event queue entries
373 *
374 * This is a policy decision.
375 */
376 #define ARBEL_NUM_EQES 4
377
378
379 /** An Arbel resource bitmask */
380 typedef uint32_t arbel_bitmask_t;
381
382 /** Size of an Arbel resource bitmask */
383 #define ARBEL_BITMASK_SIZE(max_entries) \
384 ( ( (max_entries) + ( 8 * sizeof ( arbel_bitmask_t ) ) - 1 ) / \
385 ( 8 * sizeof ( arbel_bitmask_t ) ) )
386
387 /** An Arbel device */
388 struct arbel {
389 /** PCI configuration registers */
390 void *config;
391 /** PCI user Access Region */
392 void *uar;
393 /** Event queue consumer index doorbells */
394 void *eq_ci_doorbells;
395
396 /** Command input mailbox */
397 void *mailbox_in;
398 /** Command output mailbox */
399 void *mailbox_out;
400
401 /** Firmware area in external memory */
402 userptr_t firmware_area;
403 /** ICM size */
404 size_t icm_len;
405 /** ICM AUX size */
406 size_t icm_aux_len;
407 /** ICM area */
408 userptr_t icm;
409
410 /** Event queue */
411 struct arbel_event_queue eq;
412 /** Doorbell records */
413 union arbelprm_doorbell_record *db_rec;
414 /** Reserved LKey
415 *
416 * Used to get unrestricted memory access.
417 */
418 unsigned long reserved_lkey;
419
420 /** Completion queue in-use bitmask */
421 arbel_bitmask_t cq_inuse[ ARBEL_BITMASK_SIZE ( ARBEL_MAX_CQS ) ];
422 /** Queue pair in-use bitmask */
423 arbel_bitmask_t qp_inuse[ ARBEL_BITMASK_SIZE ( ARBEL_MAX_QPS ) ];
424
425 /** Device limits */
426 struct arbel_dev_limits limits;
427
428 /** Infiniband devices */
429 struct ib_device *ibdev[ARBEL_NUM_PORTS];
430 };
431
432 /** Global protection domain */
433 #define ARBEL_GLOBAL_PD 0x123456
434
435 /** Memory key prefix */
436 #define ARBEL_MKEY_PREFIX 0x77000000UL
437
438 /*
439 * HCA commands
440 *
441 */
442
443 #define ARBEL_HCR_BASE 0x80680
444 #define ARBEL_HCR_REG(x) ( ARBEL_HCR_BASE + 4 * (x) )
445 #define ARBEL_HCR_MAX_WAIT_MS 2000
446 #define ARBEL_MBOX_ALIGN 4096
447 #define ARBEL_MBOX_SIZE 512
448
449 /* HCA command is split into
450 *
451 * bits 11:0 Opcode
452 * bit 12 Input uses mailbox
453 * bit 13 Output uses mailbox
454 * bits 22:14 Input parameter length (in dwords)
455 * bits 31:23 Output parameter length (in dwords)
456 *
457 * Encoding the information in this way allows us to cut out several
458 * parameters to the arbel_command() call.
459 */
460 #define ARBEL_HCR_IN_MBOX 0x00001000UL
461 #define ARBEL_HCR_OUT_MBOX 0x00002000UL
462 #define ARBEL_HCR_OPCODE( _command ) ( (_command) & 0xfff )
463 #define ARBEL_HCR_IN_LEN( _command ) ( ( (_command) >> 12 ) & 0x7fc )
464 #define ARBEL_HCR_OUT_LEN( _command ) ( ( (_command) >> 21 ) & 0x7fc )
465
466 /** Build HCR command from component parts */
467 #define ARBEL_HCR_INOUT_CMD( _opcode, _in_mbox, _in_len, \
468 _out_mbox, _out_len ) \
469 ( (_opcode) | \
470 ( (_in_mbox) ? ARBEL_HCR_IN_MBOX : 0 ) | \
471 ( ( (_in_len) / 4 ) << 14 ) | \
472 ( (_out_mbox) ? ARBEL_HCR_OUT_MBOX : 0 ) | \
473 ( ( (_out_len) / 4 ) << 23 ) )
474
475 #define ARBEL_HCR_IN_CMD( _opcode, _in_mbox, _in_len ) \
476 ARBEL_HCR_INOUT_CMD ( _opcode, _in_mbox, _in_len, 0, 0 )
477
478 #define ARBEL_HCR_OUT_CMD( _opcode, _out_mbox, _out_len ) \
479 ARBEL_HCR_INOUT_CMD ( _opcode, 0, 0, _out_mbox, _out_len )
480
481 #define ARBEL_HCR_VOID_CMD( _opcode ) \
482 ARBEL_HCR_INOUT_CMD ( _opcode, 0, 0, 0, 0 )
483
484 /*
485 * Doorbell record allocation
486 *
487 * The doorbell record map looks like:
488 *
489 * ARBEL_MAX_CQS * Arm completion queue doorbell
490 * ARBEL_MAX_QPS * Send work request doorbell
491 * Group separator
492 * ...(empty space)...
493 * ARBEL_MAX_QPS * Receive work request doorbell
494 * ARBEL_MAX_CQS * Completion queue consumer counter update doorbell
495 */
496
497 #define ARBEL_MAX_DOORBELL_RECORDS 512
498 #define ARBEL_GROUP_SEPARATOR_DOORBELL ( ARBEL_MAX_CQS + ARBEL_MAX_QPS )
499
500 /**
501 * Get arm completion queue doorbell index
502 *
503 * @v cqn_offset Completion queue number offset
504 * @ret doorbell_idx Doorbell index
505 */
506 static inline unsigned int
arbel_cq_arm_doorbell_idx(unsigned int cqn_offset)507 arbel_cq_arm_doorbell_idx ( unsigned int cqn_offset ) {
508 return cqn_offset;
509 }
510
511 /**
512 * Get send work request doorbell index
513 *
514 * @v qpn_offset Queue pair number offset
515 * @ret doorbell_idx Doorbell index
516 */
517 static inline unsigned int
arbel_send_doorbell_idx(unsigned int qpn_offset)518 arbel_send_doorbell_idx ( unsigned int qpn_offset ) {
519 return ( ARBEL_MAX_CQS + qpn_offset );
520 }
521
522 /**
523 * Get receive work request doorbell index
524 *
525 * @v qpn_offset Queue pair number offset
526 * @ret doorbell_idx Doorbell index
527 */
528 static inline unsigned int
arbel_recv_doorbell_idx(unsigned int qpn_offset)529 arbel_recv_doorbell_idx ( unsigned int qpn_offset ) {
530 return ( ARBEL_MAX_DOORBELL_RECORDS - ARBEL_MAX_CQS - qpn_offset - 1 );
531 }
532
533 /**
534 * Get completion queue consumer counter doorbell index
535 *
536 * @v cqn_offset Completion queue number offset
537 * @ret doorbell_idx Doorbell index
538 */
539 static inline unsigned int
arbel_cq_ci_doorbell_idx(unsigned int cqn_offset)540 arbel_cq_ci_doorbell_idx ( unsigned int cqn_offset ) {
541 return ( ARBEL_MAX_DOORBELL_RECORDS - cqn_offset - 1 );
542 }
543
544 #endif /* _ARBEL_H */
545