Searched defs:Asr (Results 1 – 3 of 3) sorted by relevance
| /art/compiler/optimizing/ |
| D | code_generator_arm_vixl.cc | 4027 __ Asr(HighRegisterFrom(out), LowRegisterFrom(out), 31); in VisitTypeConversion() local
4369 __ Asr(temp, dividend, 31); in DivRemByPowerOfTwo() local
4375 __ Asr(out, out, ctz_imm); in DivRemByPowerOfTwo() local
4414 __ Asr(temp1, temp1, shift); in GenerateDivRemWithAnyConstant() local
4940 __ Asr(out_reg, first_reg, out_reg); in HandleShift() local
4952 __ Asr(out_reg, first_reg, shift_value); in HandleShift() local
5008 __ Asr(o_h, high, o_h); in HandleShift() local
5037 __ Asr(o_l, high, shift_value - 32); in HandleShift() local
5038 __ Asr(o_h, high, 31); in HandleShift() local
5049 __ Asr(o_h, high, 31); in HandleShift() local
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| D | code_generator_arm64.cc | 2445 __ Asr(dst, lhs, shift_value); in HandleShift() local
2455 __ Asr(dst, lhs, rhs_reg); in HandleShift() local
3307 __ Asr(out, out, ctz_imm); in DivRemByPowerOfTwo() local
3313 __ Asr(temp, dividend, bits - 1); in DivRemByPowerOfTwo() local
3359 __ Asr(temp, temp, shift); in GenerateDivRemWithAnyConstant() local
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| D | intrinsics_arm_vixl.cc | 480 __ Asr(mask, in_reg_hi, 31); in GenAbsInteger() local
489 __ Asr(mask, in_reg, 31); in GenAbsInteger() local
1662 __ Asr(temp3, temp3, 7u); // uncompressed ? 0xffff0000u : 0xff0000u. in GenerateStringCompareToLoop() local
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