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1  // Copyright 2011 the V8 project authors. All rights reserved.
2  // Use of this source code is governed by a BSD-style license that can be
3  // found in the LICENSE file.
4  
5  #ifndef V8_ARM_CONSTANTS_ARM_H_
6  #define V8_ARM_CONSTANTS_ARM_H_
7  
8  #include <stdint.h>
9  
10  #include "src/base/logging.h"
11  #include "src/base/macros.h"
12  #include "src/globals.h"
13  
14  // ARM EABI is required.
15  #if defined(__arm__) && !defined(__ARM_EABI__)
16  #error ARM EABI support is required.
17  #endif
18  
19  namespace v8 {
20  namespace internal {
21  
22  // Constant pool marker.
23  // Use UDF, the permanently undefined instruction.
24  const int kConstantPoolMarkerMask = 0xfff000f0;
25  const int kConstantPoolMarker = 0xe7f000f0;
26  const int kConstantPoolLengthMaxMask = 0xffff;
EncodeConstantPoolLength(int length)27  inline int EncodeConstantPoolLength(int length) {
28    DCHECK((length & kConstantPoolLengthMaxMask) == length);
29    return ((length & 0xfff0) << 4) | (length & 0xf);
30  }
DecodeConstantPoolLength(int instr)31  inline int DecodeConstantPoolLength(int instr) {
32    DCHECK((instr & kConstantPoolMarkerMask) == kConstantPoolMarker);
33    return ((instr >> 4) & 0xfff0) | (instr & 0xf);
34  }
35  
36  // Used in code age prologue - ldr(pc, MemOperand(pc, -4))
37  const int kCodeAgeJumpInstruction = 0xe51ff004;
38  
39  // Number of registers in normal ARM mode.
40  const int kNumRegisters = 16;
41  
42  // VFP support.
43  const int kNumVFPSingleRegisters = 32;
44  const int kNumVFPDoubleRegisters = 32;
45  const int kNumVFPRegisters = kNumVFPSingleRegisters + kNumVFPDoubleRegisters;
46  
47  // PC is register 15.
48  const int kPCRegister = 15;
49  const int kNoRegister = -1;
50  
51  // Used in embedded constant pool builder - max reach in bits for
52  // various load instructions (unsigned)
53  const int kLdrMaxReachBits = 12;
54  const int kVldrMaxReachBits = 10;
55  
56  // -----------------------------------------------------------------------------
57  // Conditions.
58  
59  // Defines constants and accessor classes to assemble, disassemble and
60  // simulate ARM instructions.
61  //
62  // Section references in the code refer to the "ARM Architecture Reference
63  // Manual" from July 2005 (available at http://www.arm.com/miscPDFs/14128.pdf)
64  //
65  // Constants for specific fields are defined in their respective named enums.
66  // General constants are in an anonymous enum in class Instr.
67  
68  // Values for the condition field as defined in section A3.2
69  enum Condition {
70    kNoCondition = -1,
71  
72    eq =  0 << 28,                 // Z set            Equal.
73    ne =  1 << 28,                 // Z clear          Not equal.
74    cs =  2 << 28,                 // C set            Unsigned higher or same.
75    cc =  3 << 28,                 // C clear          Unsigned lower.
76    mi =  4 << 28,                 // N set            Negative.
77    pl =  5 << 28,                 // N clear          Positive or zero.
78    vs =  6 << 28,                 // V set            Overflow.
79    vc =  7 << 28,                 // V clear          No overflow.
80    hi =  8 << 28,                 // C set, Z clear   Unsigned higher.
81    ls =  9 << 28,                 // C clear or Z set Unsigned lower or same.
82    ge = 10 << 28,                 // N == V           Greater or equal.
83    lt = 11 << 28,                 // N != V           Less than.
84    gt = 12 << 28,                 // Z clear, N == V  Greater than.
85    le = 13 << 28,                 // Z set or N != V  Less then or equal
86    al = 14 << 28,                 //                  Always.
87  
88    kSpecialCondition = 15 << 28,  // Special condition (refer to section A3.2.1).
89    kNumberOfConditions = 16,
90  
91    // Aliases.
92    hs = cs,                       // C set            Unsigned higher or same.
93    lo = cc                        // C clear          Unsigned lower.
94  };
95  
96  
NegateCondition(Condition cond)97  inline Condition NegateCondition(Condition cond) {
98    DCHECK(cond != al);
99    return static_cast<Condition>(cond ^ ne);
100  }
101  
102  
103  // Commute a condition such that {a cond b == b cond' a}.
CommuteCondition(Condition cond)104  inline Condition CommuteCondition(Condition cond) {
105    switch (cond) {
106      case lo:
107        return hi;
108      case hi:
109        return lo;
110      case hs:
111        return ls;
112      case ls:
113        return hs;
114      case lt:
115        return gt;
116      case gt:
117        return lt;
118      case ge:
119        return le;
120      case le:
121        return ge;
122      default:
123        return cond;
124    }
125  }
126  
127  
128  // -----------------------------------------------------------------------------
129  // Instructions encoding.
130  
131  // Instr is merely used by the Assembler to distinguish 32bit integers
132  // representing instructions from usual 32 bit values.
133  // Instruction objects are pointers to 32bit values, and provide methods to
134  // access the various ISA fields.
135  typedef int32_t Instr;
136  
137  
138  // Opcodes for Data-processing instructions (instructions with a type 0 and 1)
139  // as defined in section A3.4
140  enum Opcode {
141    AND =  0 << 21,  // Logical AND.
142    EOR =  1 << 21,  // Logical Exclusive OR.
143    SUB =  2 << 21,  // Subtract.
144    RSB =  3 << 21,  // Reverse Subtract.
145    ADD =  4 << 21,  // Add.
146    ADC =  5 << 21,  // Add with Carry.
147    SBC =  6 << 21,  // Subtract with Carry.
148    RSC =  7 << 21,  // Reverse Subtract with Carry.
149    TST =  8 << 21,  // Test.
150    TEQ =  9 << 21,  // Test Equivalence.
151    CMP = 10 << 21,  // Compare.
152    CMN = 11 << 21,  // Compare Negated.
153    ORR = 12 << 21,  // Logical (inclusive) OR.
154    MOV = 13 << 21,  // Move.
155    BIC = 14 << 21,  // Bit Clear.
156    MVN = 15 << 21   // Move Not.
157  };
158  
159  
160  // The bits for bit 7-4 for some type 0 miscellaneous instructions.
161  enum MiscInstructionsBits74 {
162    // With bits 22-21 01.
163    BX   =  1 << 4,
164    BXJ  =  2 << 4,
165    BLX  =  3 << 4,
166    BKPT =  7 << 4,
167  
168    // With bits 22-21 11.
169    CLZ  =  1 << 4
170  };
171  
172  
173  // Instruction encoding bits and masks.
174  enum {
175    H = 1 << 5,   // Halfword (or byte).
176    S6 = 1 << 6,  // Signed (or unsigned).
177    L = 1 << 20,  // Load (or store).
178    S = 1 << 20,  // Set condition code (or leave unchanged).
179    W = 1 << 21,  // Writeback base register (or leave unchanged).
180    A = 1 << 21,  // Accumulate in multiply instruction (or not).
181    B = 1 << 22,  // Unsigned byte (or word).
182    N = 1 << 22,  // Long (or short).
183    U = 1 << 23,  // Positive (or negative) offset/index.
184    P = 1 << 24,  // Offset/pre-indexed addressing (or post-indexed addressing).
185    I = 1 << 25,  // Immediate shifter operand (or not).
186    B0 = 1 << 0,
187    B4 = 1 << 4,
188    B5 = 1 << 5,
189    B6 = 1 << 6,
190    B7 = 1 << 7,
191    B8 = 1 << 8,
192    B9 = 1 << 9,
193    B10 = 1 << 10,
194    B12 = 1 << 12,
195    B16 = 1 << 16,
196    B17 = 1 << 17,
197    B18 = 1 << 18,
198    B19 = 1 << 19,
199    B20 = 1 << 20,
200    B21 = 1 << 21,
201    B22 = 1 << 22,
202    B23 = 1 << 23,
203    B24 = 1 << 24,
204    B25 = 1 << 25,
205    B26 = 1 << 26,
206    B27 = 1 << 27,
207    B28 = 1 << 28,
208  
209    // Instruction bit masks.
210    kCondMask = 15 << 28,
211    kALUMask = 0x6f << 21,
212    kRdMask = 15 << 12,  // In str instruction.
213    kCoprocessorMask = 15 << 8,
214    kOpCodeMask = 15 << 21,  // In data-processing instructions.
215    kImm24Mask = (1 << 24) - 1,
216    kImm16Mask = (1 << 16) - 1,
217    kImm8Mask = (1 << 8) - 1,
218    kOff12Mask = (1 << 12) - 1,
219    kOff8Mask = (1 << 8) - 1
220  };
221  
222  enum BarrierOption {
223    OSHLD = 0x1,
224    OSHST = 0x2,
225    OSH = 0x3,
226    NSHLD = 0x5,
227    NSHST = 0x6,
228    NSH = 0x7,
229    ISHLD = 0x9,
230    ISHST = 0xa,
231    ISH = 0xb,
232    LD = 0xd,
233    ST = 0xe,
234    SY = 0xf,
235  };
236  
237  
238  // -----------------------------------------------------------------------------
239  // Addressing modes and instruction variants.
240  
241  // Condition code updating mode.
242  enum SBit {
243    SetCC   = 1 << 20,  // Set condition code.
244    LeaveCC = 0 << 20   // Leave condition code unchanged.
245  };
246  
247  
248  // Status register selection.
249  enum SRegister {
250    CPSR = 0 << 22,
251    SPSR = 1 << 22
252  };
253  
254  
255  // Shifter types for Data-processing operands as defined in section A5.1.2.
256  enum ShiftOp {
257    LSL = 0 << 5,   // Logical shift left.
258    LSR = 1 << 5,   // Logical shift right.
259    ASR = 2 << 5,   // Arithmetic shift right.
260    ROR = 3 << 5,   // Rotate right.
261  
262    // RRX is encoded as ROR with shift_imm == 0.
263    // Use a special code to make the distinction. The RRX ShiftOp is only used
264    // as an argument, and will never actually be encoded. The Assembler will
265    // detect it and emit the correct ROR shift operand with shift_imm == 0.
266    RRX = -1,
267    kNumberOfShifts = 4
268  };
269  
270  
271  // Status register fields.
272  enum SRegisterField {
273    CPSR_c = CPSR | 1 << 16,
274    CPSR_x = CPSR | 1 << 17,
275    CPSR_s = CPSR | 1 << 18,
276    CPSR_f = CPSR | 1 << 19,
277    SPSR_c = SPSR | 1 << 16,
278    SPSR_x = SPSR | 1 << 17,
279    SPSR_s = SPSR | 1 << 18,
280    SPSR_f = SPSR | 1 << 19
281  };
282  
283  // Status register field mask (or'ed SRegisterField enum values).
284  typedef uint32_t SRegisterFieldMask;
285  
286  
287  // Memory operand addressing mode.
288  enum AddrMode {
289    // Bit encoding P U W.
290    Offset       = (8|4|0) << 21,  // Offset (without writeback to base).
291    PreIndex     = (8|4|1) << 21,  // Pre-indexed addressing with writeback.
292    PostIndex    = (0|4|0) << 21,  // Post-indexed addressing with writeback.
293    NegOffset    = (8|0|0) << 21,  // Negative offset (without writeback to base).
294    NegPreIndex  = (8|0|1) << 21,  // Negative pre-indexed with writeback.
295    NegPostIndex = (0|0|0) << 21   // Negative post-indexed with writeback.
296  };
297  
298  
299  // Load/store multiple addressing mode.
300  enum BlockAddrMode {
301    // Bit encoding P U W .
302    da           = (0|0|0) << 21,  // Decrement after.
303    ia           = (0|4|0) << 21,  // Increment after.
304    db           = (8|0|0) << 21,  // Decrement before.
305    ib           = (8|4|0) << 21,  // Increment before.
306    da_w         = (0|0|1) << 21,  // Decrement after with writeback to base.
307    ia_w         = (0|4|1) << 21,  // Increment after with writeback to base.
308    db_w         = (8|0|1) << 21,  // Decrement before with writeback to base.
309    ib_w         = (8|4|1) << 21,  // Increment before with writeback to base.
310  
311    // Alias modes for comparison when writeback does not matter.
312    da_x         = (0|0|0) << 21,  // Decrement after.
313    ia_x         = (0|4|0) << 21,  // Increment after.
314    db_x         = (8|0|0) << 21,  // Decrement before.
315    ib_x         = (8|4|0) << 21,  // Increment before.
316  
317    kBlockAddrModeMask = (8|4|1) << 21
318  };
319  
320  
321  // Coprocessor load/store operand size.
322  enum LFlag {
323    Long  = 1 << 22,  // Long load/store coprocessor.
324    Short = 0 << 22   // Short load/store coprocessor.
325  };
326  
327  
328  // NEON data type
329  enum NeonDataType {
330    NeonS8 = 0,
331    NeonS16 = 1,
332    NeonS32 = 2,
333    // Gap to make it easier to extract U and size.
334    NeonU8 = 4,
335    NeonU16 = 5,
336    NeonU32 = 6
337  };
338  
NeonU(NeonDataType dt)339  inline int NeonU(NeonDataType dt) { return static_cast<int>(dt) >> 2; }
NeonSz(NeonDataType dt)340  inline int NeonSz(NeonDataType dt) { return static_cast<int>(dt) & 0x3; }
341  
342  enum NeonListType {
343    nlt_1 = 0x7,
344    nlt_2 = 0xA,
345    nlt_3 = 0x6,
346    nlt_4 = 0x2
347  };
348  
349  enum NeonSize {
350    Neon8 = 0x0,
351    Neon16 = 0x1,
352    Neon32 = 0x2,
353    Neon64 = 0x3
354  };
355  
356  // -----------------------------------------------------------------------------
357  // Supervisor Call (svc) specific support.
358  
359  // Special Software Interrupt codes when used in the presence of the ARM
360  // simulator.
361  // svc (formerly swi) provides a 24bit immediate value. Use bits 22:0 for
362  // standard SoftwareInterrupCode. Bit 23 is reserved for the stop feature.
363  enum SoftwareInterruptCodes {
364    // transition to C code
365    kCallRtRedirected = 0x10,
366    // break point
367    kBreakpoint = 0x20,
368    // stop
369    kStopCode = 1 << 23
370  };
371  const uint32_t kStopCodeMask = kStopCode - 1;
372  const uint32_t kMaxStopCode = kStopCode - 1;
373  const int32_t  kDefaultStopCode = -1;
374  
375  
376  // Type of VFP register. Determines register encoding.
377  enum VFPRegPrecision {
378    kSinglePrecision = 0,
379    kDoublePrecision = 1,
380    kSimd128Precision = 2
381  };
382  
383  // VFP FPSCR constants.
384  enum VFPConversionMode {
385    kFPSCRRounding = 0,
386    kDefaultRoundToZero = 1
387  };
388  
389  // This mask does not include the "inexact" or "input denormal" cumulative
390  // exceptions flags, because we usually don't want to check for it.
391  const uint32_t kVFPExceptionMask = 0xf;
392  const uint32_t kVFPInvalidOpExceptionBit = 1 << 0;
393  const uint32_t kVFPOverflowExceptionBit = 1 << 2;
394  const uint32_t kVFPUnderflowExceptionBit = 1 << 3;
395  const uint32_t kVFPInexactExceptionBit = 1 << 4;
396  const uint32_t kVFPFlushToZeroMask = 1 << 24;
397  const uint32_t kVFPDefaultNaNModeControlBit = 1 << 25;
398  
399  const uint32_t kVFPNConditionFlagBit = 1 << 31;
400  const uint32_t kVFPZConditionFlagBit = 1 << 30;
401  const uint32_t kVFPCConditionFlagBit = 1 << 29;
402  const uint32_t kVFPVConditionFlagBit = 1 << 28;
403  
404  
405  // VFP rounding modes. See ARM DDI 0406B Page A2-29.
406  enum VFPRoundingMode {
407    RN = 0 << 22,   // Round to Nearest.
408    RP = 1 << 22,   // Round towards Plus Infinity.
409    RM = 2 << 22,   // Round towards Minus Infinity.
410    RZ = 3 << 22,   // Round towards zero.
411  
412    // Aliases.
413    kRoundToNearest = RN,
414    kRoundToPlusInf = RP,
415    kRoundToMinusInf = RM,
416    kRoundToZero = RZ
417  };
418  
419  const uint32_t kVFPRoundingModeMask = 3 << 22;
420  
421  enum CheckForInexactConversion {
422    kCheckForInexactConversion,
423    kDontCheckForInexactConversion
424  };
425  
426  // -----------------------------------------------------------------------------
427  // Hints.
428  
429  // Branch hints are not used on the ARM.  They are defined so that they can
430  // appear in shared function signatures, but will be ignored in ARM
431  // implementations.
432  enum Hint { no_hint };
433  
434  // Hints are not used on the arm.  Negating is trivial.
NegateHint(Hint ignored)435  inline Hint NegateHint(Hint ignored) { return no_hint; }
436  
437  
438  // -----------------------------------------------------------------------------
439  // Instruction abstraction.
440  
441  // The class Instruction enables access to individual fields defined in the ARM
442  // architecture instruction set encoding as described in figure A3-1.
443  // Note that the Assembler uses typedef int32_t Instr.
444  //
445  // Example: Test whether the instruction at ptr does set the condition code
446  // bits.
447  //
448  // bool InstructionSetsConditionCodes(byte* ptr) {
449  //   Instruction* instr = Instruction::At(ptr);
450  //   int type = instr->TypeValue();
451  //   return ((type == 0) || (type == 1)) && instr->HasS();
452  // }
453  //
454  class Instruction {
455   public:
456    enum {
457      kInstrSize = 4,
458      kInstrSizeLog2 = 2,
459      kPCReadOffset = 8
460    };
461  
462    // Helper macro to define static accessors.
463    // We use the cast to char* trick to bypass the strict anti-aliasing rules.
464    #define DECLARE_STATIC_TYPED_ACCESSOR(return_type, Name)                     \
465      static inline return_type Name(Instr instr) {                              \
466        char* temp = reinterpret_cast<char*>(&instr);                            \
467        return reinterpret_cast<Instruction*>(temp)->Name();                     \
468      }
469  
470    #define DECLARE_STATIC_ACCESSOR(Name) DECLARE_STATIC_TYPED_ACCESSOR(int, Name)
471  
472    // Get the raw instruction bits.
InstructionBits()473    inline Instr InstructionBits() const {
474      return *reinterpret_cast<const Instr*>(this);
475    }
476  
477    // Set the raw instruction bits to value.
SetInstructionBits(Instr value)478    inline void SetInstructionBits(Instr value) {
479      *reinterpret_cast<Instr*>(this) = value;
480    }
481  
482    // Extract a single bit from the instruction bits and return it as bit 0 in
483    // the result.
Bit(int nr)484    inline int Bit(int nr) const {
485      return (InstructionBits() >> nr) & 1;
486    }
487  
488    // Extract a bit field <hi:lo> from the instruction bits and return it in the
489    // least-significant bits of the result.
Bits(int hi,int lo)490    inline int Bits(int hi, int lo) const {
491      return (InstructionBits() >> lo) & ((2 << (hi - lo)) - 1);
492    }
493  
494    // Read a bit field <hi:lo>, leaving its position unchanged in the result.
BitField(int hi,int lo)495    inline int BitField(int hi, int lo) const {
496      return InstructionBits() & (((2 << (hi - lo)) - 1) << lo);
497    }
498  
499    // Static support.
500  
501    // Extract a single bit from the instruction bits and return it as bit 0 in
502    // the result.
Bit(Instr instr,int nr)503    static inline int Bit(Instr instr, int nr) {
504      return (instr >> nr) & 1;
505    }
506  
507    // Extract a bit field <hi:lo> from the instruction bits and return it in the
508    // least-significant bits of the result.
Bits(Instr instr,int hi,int lo)509    static inline int Bits(Instr instr, int hi, int lo) {
510      return (instr >> lo) & ((2 << (hi - lo)) - 1);
511    }
512  
513    // Read a bit field <hi:lo>, leaving its position unchanged in the result.
BitField(Instr instr,int hi,int lo)514    static inline int BitField(Instr instr, int hi, int lo) {
515      return instr & (((2 << (hi - lo)) - 1) << lo);
516    }
517  
518    // Accessors for the different named fields used in the ARM encoding.
519    // The naming of these accessor corresponds to figure A3-1.
520    //
521    // Two kind of accessors are declared:
522    // - <Name>Field() will return the raw field, i.e. the field's bits at their
523    //   original place in the instruction encoding.
524    //   e.g. if instr is the 'addgt r0, r1, r2' instruction, encoded as
525    //   0xC0810002 ConditionField(instr) will return 0xC0000000.
526    // - <Name>Value() will return the field value, shifted back to bit 0.
527    //   e.g. if instr is the 'addgt r0, r1, r2' instruction, encoded as
528    //   0xC0810002 ConditionField(instr) will return 0xC.
529  
530  
531    // Generally applicable fields
ConditionValue()532    inline int ConditionValue() const { return Bits(31, 28); }
ConditionField()533    inline Condition ConditionField() const {
534      return static_cast<Condition>(BitField(31, 28));
535    }
536    DECLARE_STATIC_TYPED_ACCESSOR(int, ConditionValue);
537    DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionField);
538  
TypeValue()539    inline int TypeValue() const { return Bits(27, 25); }
SpecialValue()540    inline int SpecialValue() const { return Bits(27, 23); }
541  
RnValue()542    inline int RnValue() const { return Bits(19, 16); }
543    DECLARE_STATIC_ACCESSOR(RnValue);
RdValue()544    inline int RdValue() const { return Bits(15, 12); }
545    DECLARE_STATIC_ACCESSOR(RdValue);
546  
CoprocessorValue()547    inline int CoprocessorValue() const { return Bits(11, 8); }
548    // Support for VFP.
549    // Vn(19-16) | Vd(15-12) |  Vm(3-0)
VnValue()550    inline int VnValue() const { return Bits(19, 16); }
VmValue()551    inline int VmValue() const { return Bits(3, 0); }
VdValue()552    inline int VdValue() const { return Bits(15, 12); }
NValue()553    inline int NValue() const { return Bit(7); }
MValue()554    inline int MValue() const { return Bit(5); }
DValue()555    inline int DValue() const { return Bit(22); }
RtValue()556    inline int RtValue() const { return Bits(15, 12); }
PValue()557    inline int PValue() const { return Bit(24); }
UValue()558    inline int UValue() const { return Bit(23); }
Opc1Value()559    inline int Opc1Value() const { return (Bit(23) << 2) | Bits(21, 20); }
Opc2Value()560    inline int Opc2Value() const { return Bits(19, 16); }
Opc3Value()561    inline int Opc3Value() const { return Bits(7, 6); }
SzValue()562    inline int SzValue() const { return Bit(8); }
VLValue()563    inline int VLValue() const { return Bit(20); }
VCValue()564    inline int VCValue() const { return Bit(8); }
VAValue()565    inline int VAValue() const { return Bits(23, 21); }
VBValue()566    inline int VBValue() const { return Bits(6, 5); }
VFPNRegValue(VFPRegPrecision pre)567    inline int VFPNRegValue(VFPRegPrecision pre) {
568      return VFPGlueRegValue(pre, 16, 7);
569    }
VFPMRegValue(VFPRegPrecision pre)570    inline int VFPMRegValue(VFPRegPrecision pre) {
571      return VFPGlueRegValue(pre, 0, 5);
572    }
VFPDRegValue(VFPRegPrecision pre)573    inline int VFPDRegValue(VFPRegPrecision pre) {
574      return VFPGlueRegValue(pre, 12, 22);
575    }
576  
577    // Fields used in Data processing instructions
OpcodeValue()578    inline int OpcodeValue() const {
579      return static_cast<Opcode>(Bits(24, 21));
580    }
OpcodeField()581    inline Opcode OpcodeField() const {
582      return static_cast<Opcode>(BitField(24, 21));
583    }
SValue()584    inline int SValue() const { return Bit(20); }
585      // with register
RmValue()586    inline int RmValue() const { return Bits(3, 0); }
587    DECLARE_STATIC_ACCESSOR(RmValue);
ShiftValue()588    inline int ShiftValue() const { return static_cast<ShiftOp>(Bits(6, 5)); }
ShiftField()589    inline ShiftOp ShiftField() const {
590      return static_cast<ShiftOp>(BitField(6, 5));
591    }
RegShiftValue()592    inline int RegShiftValue() const { return Bit(4); }
RsValue()593    inline int RsValue() const { return Bits(11, 8); }
ShiftAmountValue()594    inline int ShiftAmountValue() const { return Bits(11, 7); }
595      // with immediate
RotateValue()596    inline int RotateValue() const { return Bits(11, 8); }
597    DECLARE_STATIC_ACCESSOR(RotateValue);
Immed8Value()598    inline int Immed8Value() const { return Bits(7, 0); }
599    DECLARE_STATIC_ACCESSOR(Immed8Value);
Immed4Value()600    inline int Immed4Value() const { return Bits(19, 16); }
ImmedMovwMovtValue()601    inline int ImmedMovwMovtValue() const {
602        return Immed4Value() << 12 | Offset12Value(); }
603    DECLARE_STATIC_ACCESSOR(ImmedMovwMovtValue);
604  
605    // Fields used in Load/Store instructions
PUValue()606    inline int PUValue() const { return Bits(24, 23); }
PUField()607    inline int PUField() const { return BitField(24, 23); }
BValue()608    inline int  BValue() const { return Bit(22); }
WValue()609    inline int  WValue() const { return Bit(21); }
LValue()610    inline int  LValue() const { return Bit(20); }
611      // with register uses same fields as Data processing instructions above
612      // with immediate
Offset12Value()613    inline int Offset12Value() const { return Bits(11, 0); }
614      // multiple
RlistValue()615    inline int RlistValue() const { return Bits(15, 0); }
616      // extra loads and stores
SignValue()617    inline int SignValue() const { return Bit(6); }
HValue()618    inline int HValue() const { return Bit(5); }
ImmedHValue()619    inline int ImmedHValue() const { return Bits(11, 8); }
ImmedLValue()620    inline int ImmedLValue() const { return Bits(3, 0); }
621  
622    // Fields used in Branch instructions
LinkValue()623    inline int LinkValue() const { return Bit(24); }
SImmed24Value()624    inline int SImmed24Value() const { return ((InstructionBits() << 8) >> 8); }
625  
626    // Fields used in Software interrupt instructions
SvcValue()627    inline SoftwareInterruptCodes SvcValue() const {
628      return static_cast<SoftwareInterruptCodes>(Bits(23, 0));
629    }
630  
631    // Test for special encodings of type 0 instructions (extra loads and stores,
632    // as well as multiplications).
IsSpecialType0()633    inline bool IsSpecialType0() const { return (Bit(7) == 1) && (Bit(4) == 1); }
634  
635    // Test for miscellaneous instructions encodings of type 0 instructions.
IsMiscType0()636    inline bool IsMiscType0() const { return (Bit(24) == 1)
637                                             && (Bit(23) == 0)
638                                             && (Bit(20) == 0)
639                                             && ((Bit(7) == 0)); }
640  
641    // Test for a nop instruction, which falls under type 1.
IsNopType1()642    inline bool IsNopType1() const { return Bits(24, 0) == 0x0120F000; }
643  
644    // Test for a stop instruction.
IsStop()645    inline bool IsStop() const {
646      return (TypeValue() == 7) && (Bit(24) == 1) && (SvcValue() >= kStopCode);
647    }
648  
649    // Special accessors that test for existence of a value.
HasS()650    inline bool HasS()    const { return SValue() == 1; }
HasB()651    inline bool HasB()    const { return BValue() == 1; }
HasW()652    inline bool HasW()    const { return WValue() == 1; }
HasL()653    inline bool HasL()    const { return LValue() == 1; }
HasU()654    inline bool HasU()    const { return UValue() == 1; }
HasSign()655    inline bool HasSign() const { return SignValue() == 1; }
HasH()656    inline bool HasH()    const { return HValue() == 1; }
HasLink()657    inline bool HasLink() const { return LinkValue() == 1; }
658  
659    // Decode the double immediate from a vmov instruction.
660    double DoubleImmedVmov() const;
661  
662    // Instructions are read of out a code stream. The only way to get a
663    // reference to an instruction is to convert a pointer. There is no way
664    // to allocate or create instances of class Instruction.
665    // Use the At(pc) function to create references to Instruction.
At(byte * pc)666    static Instruction* At(byte* pc) {
667      return reinterpret_cast<Instruction*>(pc);
668    }
669  
670  
671   private:
672    // Join split register codes, depending on register precision.
673    // four_bit is the position of the least-significant bit of the four
674    // bit specifier. one_bit is the position of the additional single bit
675    // specifier.
VFPGlueRegValue(VFPRegPrecision pre,int four_bit,int one_bit)676    inline int VFPGlueRegValue(VFPRegPrecision pre, int four_bit, int one_bit) {
677      if (pre == kSinglePrecision) {
678        return (Bits(four_bit + 3, four_bit) << 1) | Bit(one_bit);
679      } else {
680        int reg_num = (Bit(one_bit) << 4) | Bits(four_bit + 3, four_bit);
681        if (pre == kDoublePrecision) {
682          return reg_num;
683        }
684        DCHECK_EQ(kSimd128Precision, pre);
685        DCHECK_EQ(reg_num & 1, 0);
686        return reg_num / 2;
687      }
688    }
689  
690    // We need to prevent the creation of instances of class Instruction.
691    DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction);
692  };
693  
694  
695  // Helper functions for converting between register numbers and names.
696  class Registers {
697   public:
698    // Return the name of the register.
699    static const char* Name(int reg);
700  
701    // Lookup the register number for the name provided.
702    static int Number(const char* name);
703  
704    struct RegisterAlias {
705      int reg;
706      const char* name;
707    };
708  
709   private:
710    static const char* names_[kNumRegisters];
711    static const RegisterAlias aliases_[];
712  };
713  
714  // Helper functions for converting between VFP register numbers and names.
715  class VFPRegisters {
716   public:
717    // Return the name of the register.
718    static const char* Name(int reg, bool is_double);
719  
720    // Lookup the register number for the name provided.
721    // Set flag pointed by is_double to true if register
722    // is double-precision.
723    static int Number(const char* name, bool* is_double);
724  
725   private:
726    static const char* names_[kNumVFPRegisters];
727  };
728  
729  
730  }  // namespace internal
731  }  // namespace v8
732  
733  #endif  // V8_ARM_CONSTANTS_ARM_H_
734