/external/llvm/lib/Target/X86/Disassembler/ |
D | X86Disassembler.cpp | 418 unsigned NewOpc; in translateImmediate() local 452 unsigned NewOpc; in translateImmediate() local 483 unsigned NewOpc; in translateImmediate() local
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/external/capstone/arch/X86/ |
D | X86Disassembler.c | 219 unsigned NewOpc = 0; in translateImmediate() local 242 unsigned NewOpc = 0; in translateImmediate() local
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
D | X86MCInstLower.cpp | 218 static void LowerSubReg32_Op0(MCInst &OutMI, unsigned NewOpc) { in LowerSubReg32_Op0() 223 static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) { in LowerUnaryToTwoAddr()
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D | X86InstrInfo.cpp | 2674 unsigned NewOpc = 0; in foldMemoryOperandImpl() local 2736 unsigned NewOpc = 0; in foldMemoryOperandImpl() local 2962 unsigned NewOpc = 0; in unfoldMemoryOperand() local
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMLoadStoreOptimizer.cpp | 746 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); in MergeBaseUpdateLSMultiple() local 847 unsigned NewOpc = 0; in MergeBaseUpdateLoadStore() local 1047 DebugLoc dl, unsigned NewOpc, in InsertLDR_STR() 1103 unsigned NewOpc = (isLd) in FixInvalidRegPairOp() local 1126 unsigned NewOpc = (isLd) in FixInvalidRegPairOp() local 1365 unsigned NewOpc = (isThumb2 ? ARM::t2LDMIA_RET : ARM::LDMIA_RET); in MergeReturnIntoLDM() local 1504 unsigned &NewOpc, unsigned &EvenReg, in CanFormLdStDWord() 1669 unsigned NewOpc = 0; in RescheduleOps() local
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D | Thumb2InstrInfo.cpp | 436 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; in rewriteT2FrameIndex() local 470 unsigned NewOpc = Opcode; in rewriteT2FrameIndex() local
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D | ARMExpandPseudoInsts.cpp | 974 unsigned NewOpc = ARM::VLDMDIA; in ExpandMI() local 1004 unsigned NewOpc = ARM::VSTMDIA; in ExpandMI() local 1034 unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLN32q : in ExpandMI() local
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D | Thumb1RegisterInfo.cpp | 504 unsigned NewOpc = convertToNonSPOpcode(Opcode); in rewriteFrameIndex() local
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D | ARMConstantIslandPass.cpp | 1571 unsigned NewOpc = 0; in OptimizeThumb2Instructions() local 1619 unsigned NewOpc = 0; in OptimizeThumb2Branches() local
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/external/llvm/lib/Target/ARM/ |
D | ARMLoadStoreOptimizer.cpp | 1261 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); in MergeBaseUpdateLSMultiple() local 1361 unsigned NewOpc; in MergeBaseUpdateLoadStore() local 1457 unsigned NewOpc; in MergeBaseUpdateLSDouble() local 1551 bool isDef, const DebugLoc &DL, unsigned NewOpc, in InsertLDR_STR() 1616 unsigned NewOpc = (isLd) in FixInvalidRegPairOp() local 1638 unsigned NewOpc = (isLd) in FixInvalidRegPairOp() local 1875 unsigned NewOpc = (isThumb2 ? ARM::t2LDMIA_RET : ARM::LDMIA_RET); in MergeReturnIntoLDM() local 2056 DebugLoc &dl, unsigned &NewOpc, in CanFormLdStDWord() 2221 unsigned NewOpc = 0; in RescheduleOps() local
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D | Thumb2InstrInfo.cpp | 504 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; in rewriteT2FrameIndex() local 538 unsigned NewOpc = Opcode; in rewriteT2FrameIndex() local
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D | ARMExpandPseudoInsts.cpp | 1097 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; in ExpandMI() local 1136 unsigned NewOpc; in ExpandMI() local 1380 unsigned NewOpc = ARM::VLDMDIA; in ExpandMI() local 1411 unsigned NewOpc = ARM::VSTMDIA; in ExpandMI() local
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D | ThumbRegisterInfo.cpp | 396 unsigned NewOpc = convertToNonSPOpcode(Opcode); in rewriteFrameIndex() local
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D | ARMISelLowering.cpp | 2961 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls) in LowerINTRINSIC_WO_CHAIN() local 2968 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm) in LowerINTRINSIC_WO_CHAIN() local 2977 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu) in LowerINTRINSIC_WO_CHAIN() local 2986 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins) in LowerINTRINSIC_WO_CHAIN() local 2991 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins) in LowerINTRINSIC_WO_CHAIN() local 6643 unsigned NewOpc = 0; in LowerMUL() local 8251 unsigned NewOpc = MI.getOpcode() == ARM::STRi_preidx ? ARM::STR_PRE_IMM in EmitInstrWithCustomInserter() local 8275 unsigned NewOpc; in EmitInstrWithCustomInserter() local 8529 unsigned NewOpc = convertAddSubFlagsOpcode(MI.getOpcode()); in AdjustInstrPostInstrSelection() local 9922 unsigned NewOpc = 0; in CombineBaseUpdate() local [all …]
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/external/llvm/lib/Target/X86/ |
D | X86MCInstLower.cpp | 427 unsigned NewOpc; in Lower() local 452 unsigned NewOpc; in Lower() local 615 unsigned NewOpc; in Lower() local 640 unsigned NewOpc; in Lower() local
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D | X86InstrInfo.cpp | 5258 unsigned NewOpc; in optimizeCompareInstr() local 6127 unsigned NewOpc = 0; in foldMemoryOperandImpl() local 6268 unsigned NewOpc = 0; in foldMemoryOperandImpl() local 6454 unsigned NewOpc; in unfoldMemoryOperand() local
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/external/llvm/lib/Target/Lanai/ |
D | LanaiMemAluCombiner.cpp | 252 unsigned NewOpc = mergedOpcode(MemInstr->getOpcode(), AluOffset.isImm()); in insertMergedInstruction() local
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/external/llvm/lib/Target/AArch64/ |
D | AArch64AdvSIMDScalarPass.cpp | 300 unsigned NewOpc = getTransformOpcode(OldOpc); in transformInstruction() local
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D | AArch64InstrInfo.cpp | 897 unsigned NewOpc = convertFlagSettingOpcode(CmpInstr); in optimizeCompareInstr() local 1129 unsigned NewOpc = sForm(*MI); in substituteCmpToZero() local 2932 unsigned NewOpc = convertFlagSettingOpcode(Root); in getMaddPatterns() local
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D | AArch64FrameLowering.cpp | 323 unsigned NewOpc; in convertCalleeSaveRestoreToSPPrePostIncDec() local
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonRDFOpt.cpp | 210 unsigned OpNum, NewOpc; in rewrite() local
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D | HexagonGenPredicate.cpp | 368 unsigned NewOpc = getPredForm(Opc); in convertToPredForm() local
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/external/llvm/lib/Target/Mips/ |
D | MipsInstrInfo.cpp | 397 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, in genInstrWithNewOpc()
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D | MipsLongBranch.cpp | 222 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode()); in replaceBranch() local
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | LegalizeVectorOps.cpp | 474 unsigned NewOpc; in PromoteFP_TO_INT() local
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