| /external/v8/tools/clang/rewrite_to_chrome_style/tests/ |
| D | operators-original.cc | 11 struct Op2 {}; struct
13 inline bool operator==(const Op2&, const Op2) { in operator ==()
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| D | operators-expected.cc | 11 struct Op2 {}; struct
13 inline bool operator==(const Op2&, const Op2) { in operator ==()
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| /external/capstone/arch/XCore/ |
| D | XCoreDisassembler.c | 192 static DecodeStatus Decode2OpInstruction(unsigned Insn, unsigned *Op1, unsigned *Op2) in Decode2OpInstruction()
216 unsigned *Op1, unsigned *Op2, unsigned *Op3) in Decode3OpInstruction()
309 unsigned Op1, Op2; in Decode2RInstruction() local
323 unsigned Op1, Op2; in Decode2RImmInstruction() local
337 unsigned Op1, Op2; in DecodeR2RInstruction() local
351 unsigned Op1, Op2; in Decode2RSrcDstInstruction() local
366 unsigned Op1, Op2; in DecodeRUSInstruction() local
380 unsigned Op1, Op2; in DecodeRUSBitpInstruction() local
394 unsigned Op1, Op2; in DecodeRUSSrcDstBitpInstruction() local
481 unsigned Op1, Op2; in DecodeL2RInstruction() local
[all …]
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| /external/llvm/lib/Target/XCore/Disassembler/ |
| D | XCoreDisassembler.cpp | 241 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { in Decode2OpInstruction()
259 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, in Decode3OpInstruction()
347 unsigned Op1, Op2; in Decode2RInstruction() local
360 unsigned Op1, Op2; in Decode2RImmInstruction() local
373 unsigned Op1, Op2; in DecodeR2RInstruction() local
386 unsigned Op1, Op2; in Decode2RSrcDstInstruction() local
400 unsigned Op1, Op2; in DecodeRUSInstruction() local
413 unsigned Op1, Op2; in DecodeRUSBitpInstruction() local
426 unsigned Op1, Op2; in DecodeRUSSrcDstBitpInstruction() local
511 unsigned Op1, Op2; in DecodeL2RInstruction() local
[all …]
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetSelectionDAGInfo.h | 59 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemcpy()
76 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemmove()
92 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemset()
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| /external/llvm/include/llvm/CodeGen/ |
| D | SelectionDAGTargetInfo.h | 51 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy()
67 SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemmove()
80 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset()
92 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp()
129 SDValue Op1, SDValue Op2, in EmitTargetCodeForStrcmp()
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| /external/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiMCCodeEmitter.cpp | 145 const MCOperand Op2 = Inst.getOperand(2); in adjustPqBits() local
193 const MCOperand Op2 = Inst.getOperand(OpNo + 1); in getRiMemoryOpValue() local
225 const MCOperand Op2 = Inst.getOperand(OpNo + 1); in getRrMemoryOpValue() local
264 const MCOperand Op2 = Inst.getOperand(OpNo + 1); in getSplsOpValue() local
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| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.cpp | 93 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local
111 uint32_t Op2 = Bits & 0x7; in genericRegisterString() local
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiMemAluCombiner.cpp | 170 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) { in isSameOperand()
295 MachineOperand &Op2 = AluIter->getOperand(2); in isSuitableAluInstr() local
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 816 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; in ParseInstruction() local
829 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; in ParseInstruction() local
843 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; in ParseInstruction() local
856 X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]); in ParseInstruction() local
886 X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]); in ParseInstruction() local
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| /external/llvm/lib/Target/BPF/MCTargetDesc/ |
| D | BPFMCCodeEmitter.cpp | 162 MCOperand Op2 = MI.getOperand(2); in getMemoryOpValue() local
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| /external/swiftshader/third_party/LLVM/lib/Target/PTX/InstPrinter/ |
| D | PTXInstPrinter.cpp | 143 const MCOperand &Op2 = MI->getOperand(OpNo+1); in printMemOperand() local
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyPeephole.cpp | 151 const auto &Op2 = MI.getOperand(2); in runOnMachineFunction() local
|
| /external/llvm/lib/IR/ |
| D | ProfileSummary.cpp | 134 ConstantAsMetadata *Op2 = in getSummaryFromMD() local
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| /external/spirv-llvm/lib/SPIRV/libSPIRV/ |
| D | SPIRVUtil.h | 404 getVec(T Op1, T Op2) { in getVec()
413 getVec(T Op1, T Op2, T Op3) { in getVec()
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| /external/capstone/arch/AArch64/ |
| D | AArch64BaseInfo.c | 633 uint32_t Op0, Op1, CRn, CRm, Op2; in A64SysRegMapper_toString() local
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| D | AArch64InstPrinter.c | 82 MCOperand *Op2 = MCInst_getOperand(MI, 2); in AArch64_printInst() local
247 MCOperand *Op2 = MCInst_getOperand(MI, 2); in AArch64_printInst() local
330 MCOperand *Op2 = MCInst_getOperand(MI, 3); in printSysAlias() local
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsISelDAGToDAG.cpp | 246 SDValue Op2 = Node->getOperand(1); in Select() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonPeephole.cpp | 286 MachineOperand Op2 = MI.getOperand(S2); in runOnMachineFunction() local
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| D | HexagonSplitDouble.cpp | 688 MachineOperand &Op2 = MI->getOperand(2); in splitCombine() local
742 MachineOperand &Op2 = MI->getOperand(2); in splitShift() local
866 MachineOperand &Op2 = MI->getOperand(2); in splitAslOr() local
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 273 SDValue Op2 = Op.getOperand(2); in ExpandVSELECT() local
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| D | SelectionDAG.cpp | 262 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, in getSetCCOrOperation()
286 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, in getSetCCAndOperation()
717 SDValue Op1, SDValue Op2, in FindModifiedNodeSlot()
4701 SDNode *SelectionDAG::UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2) { in UpdateNodeOperands()
4730 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) { in UpdateNodeOperands()
4736 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, in UpdateNodeOperands()
4743 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, in UpdateNodeOperands()
4815 SDValue Op2) { in SelectNodeTo()
4823 SDValue Op2, SDValue Op3) { in SelectNodeTo()
4873 SDValue Op1, SDValue Op2) { in SelectNodeTo()
[all …]
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 291 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, in getSetCCOrOperation()
311 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, in getSetCCAndOperation()
839 SDValue Op1, SDValue Op2, in FindModifiedNodeSlot()
5746 SDNode *SelectionDAG::UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2) { in UpdateNodeOperands()
5775 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) { in UpdateNodeOperands()
5781 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, in UpdateNodeOperands()
5788 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, in UpdateNodeOperands()
5853 SDValue Op2) { in SelectNodeTo()
5861 SDValue Op2, SDValue Op3) { in SelectNodeTo()
5909 SDValue Op1, SDValue Op2) { in SelectNodeTo()
[all …]
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 69 const MCOperand &Op2 = MI->getOperand(2); in printInst() local
162 const MCOperand &Op2 = MI->getOperand(2); in printInst() local
738 const MCOperand &Op2 = MI->getOperand(3); in printSysAlias() local
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| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| D | PTXISelLowering.cpp | 151 SDValue Op2 = Op.getOperand(2); in LowerSETCC() local
|