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Searched defs:RS (Results 1 – 25 of 71) sorted by relevance

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/external/valgrind/none/tests/mips64/
Dmacro_int.h1 #define TEST1(instruction, RSval, RTval, RD, RS, RT) \ argument
19 #define TEST2(instruction, RSval, imm, RT, RS) \ argument
35 #define TEST3(instruction, RSval, RD, RS) \ argument
51 #define TEST4(instruction, RSval, RTval, RS, RT) \ argument
71 #define TEST5(instruction, RSval, RTval, RS, RT) \ argument
Dbranches.c130 #define TESTINST4(instruction, RDval, RSval, RTval, RD, RS, RT) \ argument
153 #define TESTINST5(instruction, RDval, RSval, RD, RS) \ argument
175 #define TESTINST6(instruction, RDval, RSval, RD, RS) \ argument
201 #define TESTINST4l(instruction, RDval, RSval, RTval, RD, RS, RT) \ argument
224 #define TESTINST5l(instruction, RDval, RSval, RD, RS) \ argument
246 #define TESTINST6l(instruction, RDval, RSval, RD, RS) \ argument
Dbranch_and_jump_instructions.c107 #define TEST3(instruction, RDval, RSval, RTval, RD, RS, RT) \ argument
130 #define TEST4(instruction, RDval, RSval, RD, RS) \ argument
152 #define TEST5(instruction, RDval, RSval, RD, RS) \ argument
Dcvm_ins.c70 #define TESTINST1(instruction, RSVal, RT, RS, p, lenm1) \ argument
85 #define TESTINST2(instruction, RSVal, RTval, RD, RS, RT) \ argument
101 #define TESTINST3(instruction, RSVal, RT, RS, imm) \ argument
Dload_store_multiple.c23 #define TESTINST1(instruction, RTval, offset, RT, RS) \ argument
53 #define TESTINSTsw(RTval, offset, RT, RS) \ argument
Dmove_instructions.c178 #define TEST5(instruction, RDval, RSval, RD, RS) \ argument
/external/valgrind/none/tests/mips32/
Dmips32_dsp.c76 #define TESTDSPINST_RD_RS_RT_DSPC(instruction, RSval, RTval, RD, RS, RT) \ argument
119 #define TESTDSPINST_RS_RT_DSPC(instruction, RSval, RTval, RS, RT) \ argument
137 #define TESTDSPINST_RD_RS_RT_NODSPC(instruction, RSval, RTval, RD, RS, RT) \ argument
155 #define TESTDSPINST_AC_RS_RT_DSPC(instruction, ac, RSval, RTval, HIval, LOval, \ argument
183 #define TESTDSPINST_AC_RS_RT_NODSPC(instruction, ac, RSval, RTval, HIval, \ argument
230 #define TESTDSPINST_EXTV(instruction, ac, RT, HIval, LOval, RS, RSval, pos) \ argument
254 #define TESTDSPINST_INSV(instruction, RTval, RSval, RT, RS, _pos, _size) \ argument
275 #define TESTDSPINST_LWX(index, RT, RS) \ argument
290 #define TESTDSPINST_LHX(index, RT, RS) \ argument
305 #define TESTDSPINST_LBUX(index, RT, RS) \ argument
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Dmips32_dspr2.c92 #define TESTDSPINST_RD_RS_RT_DSPC(instruction, RSval, RTval, RD, RS, RT) \ argument
134 #define TESTDSPINST_RS_RT_DSPC(instruction, RSval, RTval, RS, RT) \ argument
152 #define TESTDSPINST_RD_RS_RT_NODSPC(instruction, RSval, RTval, RD, RS, RT) \ argument
170 #define TESTDSPINST_AC_RS_RT_DSPC(instruction, ac, RSval, RTval, HIval, LOval, \ argument
245 #define TESTDSPINST_EXTV(instruction, ac, RT, HIval, LOval, RS, RSval, pos) \ argument
269 #define TESTDSPINST_INSV(instruction, RTval, RSval, RT, RS, _pos, _size) \ argument
290 #define TESTDSPINST_LWX(index, RT, RS) \ argument
305 #define TESTDSPINST_LHX(index, RT, RS) \ argument
320 #define TESTDSPINST_LBUX(index, RT, RS) \ argument
355 #define TESTDSPINST_MTHLIP(instruction, ac, HIval, LOval, RSval, RS, pos) \ argument
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DMIPS32int.c3 #define TESTINST1(instruction, RSval, RTval, RD, RS, RT) \ argument
20 #define TESTINST2(instruction, RSval, imm, RT, RS) \ argument
35 #define TESTINST3(instruction, RSval, RD, RS) \ argument
50 #define TESTINST3a(instruction, RSval, RTval, RS, RT) \ argument
71 #define TESTINST4(instruction, RTval, RSval, RT, RS, pos, size) \ argument
Dbranches.c129 #define TESTINST4(instruction, RDval, RSval, RTval, RD, RS, RT) \ argument
153 #define TESTINST5(instruction, RDval, RSval, RD, RS) \ argument
176 #define TESTINST6(instruction, RDval, RSval, RD, RS) \ argument
203 #define TESTINST4l(instruction, RDval, RSval, RTval, RD, RS, RT) \ argument
227 #define TESTINST5l(instruction, RDval, RSval, RD, RS) \ argument
250 #define TESTINST6l(instruction, RDval, RSval, RD, RS) \ argument
DLoadStore1.c24 #define TESTINST1(instruction, RTval, offset, RT, RS) \ argument
54 #define TESTINSTsw(RTval, offset, RT, RS) \ argument
DLoadStore.c24 #define TESTINST1(instruction, RTval, offset, RT, RS) \ argument
54 #define TESTINSTsw(RTval, offset, RT, RS) \ argument
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCJITInfo.cpp27 #define BUILD_ADDIS(RD,RS,IMM16) \ argument
29 #define BUILD_ORI(RD,RS,UIMM16) \ argument
31 #define BUILD_ORIS(RD,RS,UIMM16) \ argument
33 #define BUILD_RLDICR(RD,RS,SH,ME) \ argument
36 #define BUILD_MTSPR(RS,SPR) \ argument
45 #define BUILD_SLDI(RD,RS,IMM6) BUILD_RLDICR(RD,RS,IMM6,63-IMM6) argument
46 #define BUILD_MTCTR(RS) BUILD_MTSPR(RS,9) argument
/external/valgrind/none/tests/arm/
Dv6intARM.c70 #define TESTINST4(instruction, RMval, RNval, RSval, RD, RM, RN, RS, carryin) \ argument
100 #define TESTINST4_2OUT(instruction, RDval, RD2val, RMval, RSval, RD, RD2, RM, RS, carryin) \ argument
Dv6media.c79 #define TESTINST4(instruction, RMval, RNval, RSval, RD, RM, RN, RS, carryin) \ argument
109 #define TESTINST4_2OUT(instruction, RDval, RD2val, RMval, RSval, RD, RD2, RM, RS, carryin) \ argument
Dv6intThumb.c162 #define TESTINST4(instruction, RMval, RNval, RSval, RD, RM, RN, RS, cvin) \ argument
190 #define TESTINST4_2OUT(instruction, RDval, RD2val, RMval, RSval, RD, RD2, RM, RS, cvin) \ argument
/external/llvm/include/llvm/DebugInfo/DWARF/
DDWARFCompileUnit.h20 const DWARFDebugAbbrev *DA, StringRef RS, StringRef SS, in DWARFCompileUnit()
DDWARFTypeUnit.h23 const DWARFDebugAbbrev *DA, StringRef RS, StringRef SS, in DWARFTypeUnit()
DDWARFUnit.h82 const DWARFDebugAbbrev *DA, StringRef RS, StringRef SS, in parseImpl()
164 void setRangesSection(StringRef RS, uint32_t Base) { in setRangesSection()
/external/clang/lib/StaticAnalyzer/Checkers/
DReturnPointerRangeChecker.cpp35 void ReturnPointerRangeChecker::checkPreStmt(const ReturnStmt *RS, in checkPreStmt()
DMallocChecker.cpp94 static RefState getAllocatedOfSizeZero(const RefState *RS) { in getAllocatedOfSizeZero()
104 static RefState getEscaped(const RefState *RS) { in getEscaped()
905 const RefState *RS = State->get<RegionState>(Sym); in ProcessZeroAllocation() local
1506 const RefState *RS = C.getState()->get<RegionState>(Sym); in getCheckIfTracked() local
1673 const RefState *RS, in ReportMismatchedDealloc()
2065 const RefState *RS = C.getState()->get<RegionState>(Sym); in reportLeak() local
2133 RegionStateTy RS = state->get<RegionState>(); in checkDeadSymbols() local
2294 const RefState *RS = C.getState()->get<RegionState>(Sym); in isReleased() local
2313 if (const RefState *RS = C.getState()->get<RegionState>(Sym)) { in checkUseZeroAllocated() local
2346 RegionStateTy RS = state->get<RegionState>(); in evalAssume() local
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DReturnUndefChecker.cpp39 void ReturnUndefChecker::checkPreStmt(const ReturnStmt *RS, in checkPreStmt()
/external/llvm/lib/CodeGen/
DShrinkWrap.cpp273 RegScavenger *RS) { in updateSaveRestorePoints()
443 std::unique_ptr<RegScavenger> RS( in runOnMachineFunction() local
/external/clang/tools/scan-build-py/libscanbuild/
Dintercept.py42 RS = chr(0x1e) variable
/external/llvm/lib/Target/XCore/
DXCoreRegisterInfo.cpp96 int Offset, RegScavenger *RS ) { in InsertFPConstInst()
164 unsigned Reg, int Offset, RegScavenger *RS ) { in InsertSPConstInst()

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