| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | RegisterClassInfo.h | 41 OwningArrayPtr<RCInfo> RegClass; variable
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| D | MachineRegisterInfo.cpp | 97 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ in createVirtualRegister()
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| /external/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.cpp | 51 #define DECODE_OPERAND2(RegClass, DecName) \ argument
60 #define DECODE_OPERAND(RegClass) DECODE_OPERAND2(RegClass, RegClass) argument
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | RegisterScavenging.h | 120 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { in scavengeRegister()
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| /external/llvm/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 45 std::unique_ptr<RCInfo[]> RegClass; variable
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| D | RegisterScavenging.h | 145 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { in scavengeRegister()
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| /external/swiftshader/third_party/LLVM/lib/Target/ |
| D | TargetInstrInfo.cpp | 36 short RegClass = MCID.OpInfo[OpNum].RegClass; in getRegClass() local
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceTypes.h | 36 enum RegClass : uint8_t { enum
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| /external/capstone/ |
| D | MCInstrDesc.h | 63 int16_t RegClass; member
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| /external/llvm/lib/CodeGen/ |
| D | RenameIndependentSubregs.cpp | 134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in INITIALIZE_PASS_DEPENDENCY() local
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| D | MachineRegisterInfo.cpp | 95 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ in createVirtualRegister()
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| D | TargetInstrInfo.cpp | 51 short RegClass = MCID.OpInfo[OpNum].RegClass; in getRegClass() local
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| D | LiveIntervalAnalysis.cpp | 1562 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in splitSeparateComponents() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1598 SDValue RegClass = in createGPRPairNode() local
1609 SDValue RegClass = in createSRegPairNode() local
1620 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl, in createDRegPairNode() local
1631 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQRegPairNode() local
1643 SDValue RegClass = in createQuadSRegsNode() local
1658 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQuadDRegsNode() local
1673 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl, in createQuadQRegsNode() local
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| D | ARMLoadStoreOptimizer.cpp | 551 unsigned ARMLoadStoreOpt::findFreeReg(const TargetRegisterClass &RegClass) { in findFreeReg()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1454 SDValue RegClass = in PairSRegs() local
1466 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32); in PairDRegs() local
1477 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32); in PairQRegs() local
1489 SDValue RegClass = in QuadSRegs() local
1505 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32); in QuadDRegs() local
1520 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, MVT::i32); in QuadQRegs() local
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegStackify.cpp | 547 const auto *RegClass = MRI.getRegClass(Reg); in MoveAndTeeForMultiUse() local
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 200 int RegClass = Desc.OpInfo[OpIdx].RegClass; in getOperandRegClass() local
315 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in Select() local
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| D | SIInstrInfo.cpp | 1672 int RegClass = Desc.OpInfo[i].RegClass; in verifyInstruction() local
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| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| D | CodeGenDAGPatterns.cpp | 1250 Record *RegClass = R->getValueAsDef("RegClass"); in getImplicitType() local
1538 Record *RegClass = ResultNode->getValueAsDef("RegClass"); in ApplyTypeConstraints() local
1601 Record *RegClass = OperandNode->getValueAsDef("RegClass"); in ApplyTypeConstraints() local
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| /external/llvm/lib/Target/X86/ |
| D | X86FrameLowering.cpp | 549 const TargetRegisterClass *RegClass = &X86::GR64RegClass; in emitStackProbeInline() local
2525 auto &RegClass = in adjustStackWithPops() local
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 1274 for (auto &RegClass : RegClasses) { in computeSubRegLaneMasks() local
1334 for (auto &RegClass : RegBank.getRegClasses()) { in computeUberSets() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAG.cpp | 1101 SDValue RegClass = CurDAG->getTargetConstant(Hexagon::DoubleRegsRegClassID, in SelectBitOp() local
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 1792 const TargetRegisterClass *RegClass = in constrainOperandRegClass() local
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| D | ScheduleDAGRRList.cpp | 279 unsigned &RegClass, unsigned &Cost, in GetCostForDef()
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