| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerMIPS32.cpp | 209 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRsRt() local
222 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRtRsImm16() local
237 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRtRsImm16Rel() local
259 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitFtRsImm16() local
285 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRdRsRt() local
528 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "clz"); in clz() local
656 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "jalr"); in jalr() local
820 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "pseudo-move"); in move() local
837 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "movf"); in movf() local
872 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "movt"); in movt() local
[all …]
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| D | IceAssemblerARM32.cpp | 344 IValueT Rs) { in encodeShiftRotateReg()
393 IValueT Rs; in encodeOperand() local
1128 IValueT Rn, IValueT Rm, IValueT Rs, in emitMulOp()
1717 IValueT Rs = encodeGPRegister(OpSrc1, "Rs", InstName); in emitShift() local
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| /external/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 602 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeAddiGroupBranch() local
632 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP35GroupBranchMMR6() local
672 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeDaddiGroupBranch() local
702 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP37GroupBranchMMR6() local
743 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBlezlGroupBranch() local
788 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBgtzlGroupBranch() local
830 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBgtzGroupBranch() local
879 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBlezGroupBranch() local
2287 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodeBgtzGroupBranchMMR6() local
2333 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodeBlezGroupBranchMMR6() local
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| /external/capstone/arch/Mips/ |
| D | MipsDisassembler.c | 536 uint32_t Rs = fieldFromInstruction(insn, 21, 5); in DecodeAddiGroupBranch_4() local
572 uint32_t Rs = fieldFromInstruction(insn, 21, 5); in DecodeDaddiGroupBranch_4() local
609 uint32_t Rs = fieldFromInstruction(insn, 21, 5); in DecodeBlezlGroupBranch_4() local
651 uint32_t Rs = fieldFromInstruction(insn, 21, 5); in DecodeBgtzlGroupBranch_4() local
689 uint32_t Rs = fieldFromInstruction(insn, 21, 5); in DecodeBgtzGroupBranch_4() local
735 uint32_t Rs = fieldFromInstruction(insn, 21, 5); in DecodeBlezGroupBranch_4() local
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| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1844 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1863 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1882 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1904 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1943 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1953 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1995 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
2014 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
2151 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCCompound.cpp | 207 MCOperand Rs, Rt; in getCompoundInsn() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonSplitDouble.cpp | 122 const USet &Rs = I.second; in isInduction() local
431 USet &Rs) { in collectIndRegsForLoop()
537 USet Rs; in collectIndRegs() local
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| D | HexagonAsmPrinter.cpp | 365 MCOperand &Rs = Inst.getOperand(1); in HexagonProcessInstruction() local
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| D | HexagonBitTracker.cpp | 225 uint16_t BW, bool Odd) -> BT::RegisterCell { in evaluate()
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| D | HexagonBitSimplify.cpp | 1782 const BitTracker::RegisterCell &RC, BitTracker::RegisterRef &Rs, in matchPackhl()
1914 BitTracker::RegisterRef Rs, Rt; in genPackhl() local
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| D | RDFGraph.cpp | 1333 const auto &Rs = RefM[DBA.Id]; in recordDefsForDF() local
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| D | HexagonGenInsert.cpp | 1232 void IFOrdering::stats(const RegisterSet &Rs, unsigned &Size, unsigned &Zero, in stats()
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| D | HexagonFrameLowering.cpp | 2203 unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg(); in expandAlloca() local
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| D | HexagonInstrInfo.cpp | 1240 unsigned Rs = Op2.getReg(); in expandPostRAPseudo() local
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| /external/eigen/Eigen/src/UmfPackSupport/ |
| D | UmfPackSupport.h | 109 … int P[], int Q[], double Dx[], int *do_recip, double Rs[], void *Numeric) in umfpack_get_numeric()
115 … int P[], int Q[], std::complex<double> Dx[], int *do_recip, double Rs[], void *Numeric) in umfpack_get_numeric()
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| /external/mesa3d/src/mesa/swrast/ |
| D | s_blend.c | 480 const GLfloat Rs = rgba[i][RCOMP]; in blend_general_float() local
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| /external/v8/src/arm64/ |
| D | assembler-arm64.h | 1731 static Instr Rs(CPURegister rs) { in Rs() function
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| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 2620 static Instr Rs(CPURegister rs) { in Rs() function
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| /external/capstone/arch/AArch64/ |
| D | AArch64Disassembler.c | 1196 unsigned Rs = fieldFromInstruction(insn, 16, 5); in DecodeExclusiveLdStInstruction() local
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| /external/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 1087 unsigned Rs = fieldFromInstruction(insn, 16, 5); in DecodeExclusiveLdStInstruction() local
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCCodeEmitter.cpp | 1108 unsigned Rs = MO1.getReg(); in getSORegRegOpValue() local
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMCodeEmitter.cpp | 931 unsigned Rs = MO1.getReg(); in getMachineSoRegOpValue() local
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCCodeEmitter.cpp | 1336 unsigned Rs = MO1.getReg(); in getSORegRegOpValue() local
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1062 unsigned Rs = fieldFromInstruction32(Val, 8, 4); in DecodeSORegRegOperand() local
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| /external/capstone/arch/ARM/ |
| D | ARMDisassembler.c | 1206 unsigned Rs = fieldFromInstruction_4(Val, 8, 4); in DecodeSORegRegOperand() local
|