| /external/llvm/lib/Target/AArch64/ |
| D | AArch64AdvSIMDScalarPass.cpp | 112 static bool isGPR64(unsigned Reg, unsigned SubReg, in isGPR64()
121 static bool isFPR64(unsigned Reg, unsigned SubReg, in isFPR64()
137 unsigned &SubReg) { in getSrcFromCopy()
253 unsigned SubReg; in isProfitableToTransform() local
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| D | AArch64ISelDAGToDAG.cpp | 556 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32); in narrowIfNeeded() local
765 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32); in Widen() local
1118 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32); in tryIndexedLoad() local
1735 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32); in tryBitfieldExtractOp() local
2638 unsigned SubReg; in Select() local
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| /external/llvm/lib/CodeGen/ |
| D | LiveVariables.cpp | 198 unsigned SubReg = *SubRegs; in FindLastPartialDef() local
252 unsigned SubReg = *SubRegs; in HandlePhysRegUse() local
291 unsigned SubReg = *SubRegs; in FindLastRefOrPartRef() local
340 unsigned SubReg = *SubRegs; in HandlePhysRegKill() local
371 unsigned SubReg = *SubRegs; in HandlePhysRegKill() local
453 unsigned SubReg = *SubRegs; in HandlePhysRegDef() local
475 unsigned SubReg = *SubRegs; in HandlePhysRegDef() local
493 unsigned SubReg = *SubRegs; in UpdatePhysRegDefs() local
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| D | DetectDeadLanes.cpp | 180 unsigned SubReg = MI.getOperand(2).getImm(); in isCrossCopy() local
430 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes() local
463 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput() local
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| D | LiveRangeCalc.cpp | 65 unsigned SubReg = MO.getSubReg(); in calculate() local
175 unsigned SubReg = MO.getSubReg(); in extendToUses() local
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| D | LiveIntervalAnalysis.cpp | 522 unsigned SubReg = MO.getSubReg(); in shrinkToUses() local
956 unsigned SubReg = MO.getSubReg(); in updateAllRanges() local
1319 unsigned SubReg = MO.getSubReg(); in findLastUseBefore() local
1421 unsigned SubReg = MO.getSubReg(); in repairOldRegInRange() local
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| D | MachineInstrBundle.cpp | 188 unsigned SubReg = *SubRegs; in finalizeBundle() local
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| D | VirtRegMap.cpp | 405 unsigned SubReg = MO.getSubReg(); in rewrite() local
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| D | PeepholeOptimizer.cpp | 225 ValueTrackerResult(unsigned Reg, unsigned SubReg) : Inst(nullptr) { in ValueTrackerResult()
616 bool PeepholeOptimizer::findNextSource(unsigned Reg, unsigned SubReg, in findNextSource()
1261 unsigned Reg, SubReg, CopyDefReg, CopyDefSubReg; in optimizeUncoalescableCopy() local
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| D | LiveRangeEdit.cpp | 227 unsigned SubReg = MO.getSubReg(); in useIsKill() local
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsExpandPseudo.cpp | 92 const unsigned* SubReg = in ExpandBuildPairF64() local
108 const unsigned* SubReg = TM.getRegisterInfo()->getSubRegisters(SrcReg); in ExpandExtractElementF64() local
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.cpp | 464 unsigned SubReg = NumSubRegs > 1 ? in buildScratchLoadStore() local
525 unsigned SubReg = getPhysRegSubReg(SuperReg, in eliminateFrameIndex() local
590 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(), in eliminateFrameIndex() local
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| D | SIFixSGPRCopies.cpp | 200 unsigned SubReg = CopyUse.getOperand(1).getSubReg(); in foldVGPRCopyIntoRegSequence() local
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| D | R600OptimizeVectorRegisters.cpp | 193 unsigned SubReg = (*It).first; in RebuildVector() local
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| D | SILowerControlFlow.cpp | 600 unsigned SubReg = TRI->getSubReg(VecReg, AMDGPU::sub0); in computeIndirectRegAndOffset() local
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| D | SIInstrInfo.cpp | 1008 unsigned SubReg = Src0.getSubReg(); in commuteInstructionImpl() local
1910 unsigned SubReg = MRI.createVirtualRegister(SubRC); in buildExtractSubReg() local
1950 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC, in buildExtractSubRegOrImm() local
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 921 unsigned SubReg, in shouldCoalesce()
954 unsigned SubReg; variable
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | MachineOperand.h | 62 unsigned char SubReg; variable
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 618 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx); in expandExtractElementF64() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 785 unsigned SubReg, in shouldCoalesce()
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| /external/llvm/lib/CodeGen/MIRParser/ |
| D | MIParser.cpp | 873 bool MIParser::parseSubRegisterIndex(unsigned &SubReg) { in parseSubRegisterIndex()
961 unsigned SubReg = 0; in parseRegisterOperand() local
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 578 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap); in EmitRegSequence() local
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| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 41 CodeGenRegister *SubReg; member
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 418 const CodeGenRegister *SubReg = I->second; in computeSecondarySubRegs() local
1790 CodeGenRegister *SubReg = S->second; in computeRegUnitLaneMasks() local
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 627 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap); in EmitRegSequence() local
|