1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "brw_context.h"
25 #include "brw_state.h"
26 #include "brw_defines.h"
27 #include "intel_batchbuffer.h"
28
29 static void
gen8_upload_hs_state(struct brw_context * brw)30 gen8_upload_hs_state(struct brw_context *brw)
31 {
32 const struct gen_device_info *devinfo = &brw->screen->devinfo;
33 const struct brw_stage_state *stage_state = &brw->tcs.base;
34 /* BRW_NEW_TESS_PROGRAMS */
35 bool active = brw->tess_eval_program;
36 /* BRW_NEW_TCS_PROG_DATA */
37 const struct brw_stage_prog_data *prog_data = stage_state->prog_data;
38 const struct brw_tcs_prog_data *tcs_prog_data =
39 brw_tcs_prog_data(stage_state->prog_data);
40
41 if (active) {
42 BEGIN_BATCH(9);
43 OUT_BATCH(_3DSTATE_HS << 16 | (9 - 2));
44 OUT_BATCH(SET_FIELD(DIV_ROUND_UP(stage_state->sampler_count, 4),
45 GEN7_HS_SAMPLER_COUNT) |
46 SET_FIELD(prog_data->binding_table.size_bytes / 4,
47 GEN7_HS_BINDING_TABLE_ENTRY_COUNT));
48 OUT_BATCH(GEN7_HS_ENABLE |
49 GEN7_HS_STATISTICS_ENABLE |
50 (devinfo->max_tcs_threads - 1) << GEN8_HS_MAX_THREADS_SHIFT |
51 SET_FIELD(tcs_prog_data->instances - 1,
52 GEN7_HS_INSTANCE_COUNT));
53 OUT_BATCH(stage_state->prog_offset);
54 OUT_BATCH(0);
55 if (prog_data->total_scratch) {
56 OUT_RELOC64(stage_state->scratch_bo,
57 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
58 ffs(stage_state->per_thread_scratch) - 11);
59 } else {
60 OUT_BATCH(0);
61 OUT_BATCH(0);
62 }
63 OUT_BATCH(GEN7_HS_INCLUDE_VERTEX_HANDLES |
64 SET_FIELD(prog_data->dispatch_grf_start_reg,
65 GEN7_HS_DISPATCH_START_GRF));
66 OUT_BATCH(0); /* MBZ */
67 ADVANCE_BATCH();
68 } else {
69 BEGIN_BATCH(9);
70 OUT_BATCH(_3DSTATE_HS << 16 | (9 - 2));
71 OUT_BATCH(0);
72 OUT_BATCH(0);
73 OUT_BATCH(0);
74 OUT_BATCH(0);
75 OUT_BATCH(0);
76 OUT_BATCH(0);
77 OUT_BATCH(0);
78 OUT_BATCH(0);
79 ADVANCE_BATCH();
80 }
81 brw->tcs.enabled = active;
82 }
83
84 const struct brw_tracked_state gen8_hs_state = {
85 .dirty = {
86 .mesa = 0,
87 .brw = BRW_NEW_BATCH |
88 BRW_NEW_BLORP |
89 BRW_NEW_TCS_PROG_DATA |
90 BRW_NEW_TESS_PROGRAMS,
91 },
92 .emit = gen8_upload_hs_state,
93 };
94