| /external/gemmlowp/meta/generators/ |
| D | zip_Nx8_neon.py | 21 def __init__(self, input_address, load, aggregator): argument
27 def GenerateZipLanes(emitter, registers, zip_lanes, input_address, stride): argument
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| D | transform_kernels_common.py | 57 def Transform(self, emitter, registers, input_address, elements, argument
103 def Transform(self, emitter, registers, input_address, elements, argument
172 def Transform(self, emitter, registers, input_address, elements, argument
253 def Transform(self, emitter, registers, input_address, elements, argument
487 def _BiasAdd(self, emitter, registers, elements, input_address, bias, argument
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| D | streams_common.py | 37 def _GenerateInputs(emitter, registers, lanes_count, input_address, stride): argument
206 elements_count, aggregators, input_address, argument
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| D | mul_Nx8_Mx8_neon.py | 20 def __init__(self, input_address): argument
165 def ReadParams(emitter, registers, input_address, elements, min_reg): argument
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| D | quantized_mul_kernels_common.py | 19 def _ReadParams(emitter, registers, input_address, elements, min_register): argument
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| D | neon_emitter.py | 717 input_address, stride): argument
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| D | neon_emitter_64.py | 1134 input_address, stride): argument
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| /external/tensorflow/tensorflow/compiler/xla/service/gpu/ |
| D | ir_emitter_unnested.cc | 1031 llvm::Value* input_address = ir_builder_.CreateAlloca(element_ir_type); in EmitReductionToScalar() local
1210 llvm::Value* input_address = ir_builder_.CreateAlloca(element_ir_type); in EmitColumnReduction() local
1454 llvm::Value* input_address = ir_builder_.CreateAlloca(element_ir_type); in EmitRowReduction() local
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| D | ir_emitter.cc | 672 llvm::Value* input_address = in HandleReduce() local
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| /external/tensorflow/tensorflow/compiler/xla/service/cpu/ |
| D | ir_emitter.cc | 1533 llvm::Value* input_address = ir_builder_.CreateBitCast( in EmitInnerLoopForVectorizedReduction() local
1803 llvm::Value* input_address = in HandleReduce() local
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