| /external/libvpx/libvpx/vpx_dsp/mips/ |
| D | idct32x32_msa.c | 44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local
128 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_odd_process_store() local
354 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct8x32_column_even_process_store() local
434 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct8x32_column_odd_process_store() local
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| D | txfm_macros_msa.h | 16 #define DOTP_CONST_PAIR(reg0, reg1, cnst0, cnst1, out0, out1) \ argument
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| D | idct16x16_msa.c | 15 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vpx_idct16_1d_rows_msa() local
109 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vpx_idct16_1d_columns_addblk_msa() local
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| /external/libyuv/files/source/ |
| D | row_msa.cc | 481 v16u8 reg0, reg1, reg2, reg3; in I422ToRGB24Row_MSA() local
570 v8u16 reg0, reg1, reg2; in I422ToARGB4444Row_MSA() local
610 v8u16 reg0, reg1, reg2; in I422ToARGB1555Row_MSA() local
774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGBToYRow_MSA() local
826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
1085 v16u8 src0, src1, src2, src3, reg0, reg1, reg2, reg3, dst0, dst1; in ARGBToUV444Row_MSA() local
1159 v4u32 reg0, reg1, reg2, reg3; in ARGBMultiplyRow_MSA() local
1237 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ARGBAttenuateRow_MSA() local
1305 v8i16 reg0, reg1, reg2; in ARGBToRGB565DitherRow_MSA() local
1373 v4u32 reg0, reg1, reg2, reg3, rgba_scale; in ARGBShadeRow_MSA() local
[all …]
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| D | rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
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| D | scale_msa.cc | 70 v8u16 reg0, reg1, reg2, reg3; in ScaleARGBRowDown2Box_MSA() local
133 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
296 v4u32 reg0, reg1, reg2, reg3; in ScaleRowDown4Box_MSA() local
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| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| D | r200_fragshader.c | 48 GLuint reg0 = 0; in r200SetFragShaderArg() local
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| /external/tensorflow/tensorflow/contrib/lite/ |
| D | model_test.cc | 164 const TfLiteRegistration& reg0 = node_and_reg0->second; in TEST() local
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| /external/v8/src/x87/ |
| D | assembler-x87.h | 689 void cmp(Register reg0, Register reg1) { cmp(reg0, Operand(reg1)); } in cmp()
774 void test(Register reg0, Register reg1) { test(reg0, Operand(reg1)); } in test()
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| /external/vixl/test/aarch64/ |
| D | test-utils-aarch64.cc | 195 bool Equal64(const Register& reg0, in Equal64()
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| /external/clang/test/OpenMP/ |
| D | taskloop_loop_messages.cpp | 19 int reg0; variable
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| D | taskloop_simd_loop_messages.cpp | 19 int reg0; variable
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| D | for_loop_messages.cpp | 19 int reg0; variable
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerX86BaseImpl.h | 2575 void AssemblerX86Base<TraitsType>::arith_int(Type Ty, GPRRegister reg0, in arith_int()
2647 void AssemblerX86Base<TraitsType>::cmp(Type Ty, GPRRegister reg0, in cmp()
3748 void AssemblerX86Base<TraitsType>::xchg(Type Ty, GPRRegister reg0, in xchg()
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| /external/v8/src/ia32/ |
| D | assembler-ia32.h | 696 void cmp(Register reg0, Register reg1) { cmp(reg0, Operand(reg1)); } in cmp()
781 void test(Register reg0, Register reg1) { test(reg0, Operand(reg1)); } in test()
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| /external/v8/src/mips/ |
| D | macro-assembler-mips.cc | 506 void MacroAssembler::GetNumberHash(Register reg0, Register scratch) { in GetNumberHash()
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| /external/v8/src/mips64/ |
| D | macro-assembler-mips64.cc | 523 void MacroAssembler::GetNumberHash(Register reg0, Register scratch) { in GetNumberHash()
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