| /art/compiler/utils/mips64/ |
| D | assembler_mips64.cc | 99 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, in EmitR()
126 void Mips64Assembler::EmitRtd(int opcode, GpuRegister rt, GpuRegister rd, in EmitRtd()
139 void Mips64Assembler::EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm) { in EmitI()
303 void Mips64Assembler::Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Addu()
307 void Mips64Assembler::Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Addiu()
311 void Mips64Assembler::Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Daddu()
315 void Mips64Assembler::Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Daddiu()
319 void Mips64Assembler::Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Subu()
323 void Mips64Assembler::Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Dsubu()
327 void Mips64Assembler::MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in MulR6()
[all …]
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| /art/compiler/utils/mips/ |
| D | assembler_mips.cc | 257 Register rt, in EmitR()
274 uint32_t MipsAssembler::EmitI(int opcode, Register rs, Register rt, uint16_t imm) { in EmitI()
454 void MipsAssembler::Addu(Register rd, Register rs, Register rt) { in Addu()
458 void MipsAssembler::Addiu(Register rt, Register rs, uint16_t imm16, MipsLabel* patcher_label) { in Addiu()
465 void MipsAssembler::Addiu(Register rt, Register rs, uint16_t imm16) { in Addiu()
469 void MipsAssembler::Subu(Register rd, Register rs, Register rt) { in Subu()
473 void MipsAssembler::MultR2(Register rs, Register rt) { in MultR2()
478 void MipsAssembler::MultuR2(Register rs, Register rt) { in MultuR2()
483 void MipsAssembler::DivR2(Register rs, Register rt) { in DivR2()
488 void MipsAssembler::DivuR2(Register rs, Register rt) { in DivuR2()
[all …]
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| /art/runtime/ |
| D | reference_table_test.cc | 80 ReferenceTable rt("test", 0, 11); in TEST_F() local
276 ReferenceTable rt("test", 0, 20); in TEST_F() local
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| /art/runtime/interpreter/mterp/mips/ |
| D | header.S | 160 #define SEB(rd, rt) \ argument
162 #define SEH(rd, rt) \ argument
167 #define SEB(rd, rt) \ argument
170 #define SEH(rd, rt) \ argument
188 #define JR(rt) \ argument
190 #define LSA(rd, rs, rt, sa) \ argument
197 #define JR(rt) \ argument
199 #define LSA(rd, rs, rt, sa) \ argument
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| /art/disassembler/ |
| D | disassembler_mips.cc | 522 uint32_t rt = (instruction >> 16) & 0x1f; // I-type, R-type. in Dump() local
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| /art/runtime/interpreter/mterp/out/ |
| D | mterp_mips.S | 167 #define SEB(rd, rt) \ argument
169 #define SEH(rd, rt) \ argument
174 #define SEB(rd, rt) \ argument
177 #define SEH(rd, rt) \ argument
195 #define JR(rt) \ argument
197 #define LSA(rd, rs, rt, sa) \ argument
204 #define JR(rt) \ argument
206 #define LSA(rd, rs, rt, sa) \ argument
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| /art/compiler/optimizing/ |
| D | loop_optimization.cc | 927 HInstruction* rt = Insert( in Vectorize() local
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| D | code_generator_arm_vixl.cc | 134 static inline bool CanEmitNarrowLdr(vixl32::Register rt, vixl32::Register rn, uint32_t offset) { in CanEmitNarrowLdr()
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